OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [m68hc11/] [Makefile.in] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 131 jeremybenn
#    Makefile template for Configure for the 68HC11 sim library.
2
#    Copyright (C) 1999, 2000, 2001, 2007, 2008 Free Software Foundation, Inc.
3
#    Written by Cygnus Support.
4
#
5
# This program is free software; you can redistribute it and/or modify
6
# it under the terms of the GNU General Public License as published by
7
# the Free Software Foundation; either version 3 of the License, or
8
# (at your option) any later version.
9
#
10
# This program is distributed in the hope that it will be useful,
11
# but WITHOUT ANY WARRANTY; without even the implied warranty of
12
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
# GNU General Public License for more details.
14
#
15
# You should have received a copy of the GNU General Public License
16
# along with this program.  If not, see .
17
 
18
## COMMON_PRE_CONFIG_FRAG
19
 
20
M68HC11_OBJS = interp.o m68hc11int.o m68hc12int.o \
21
                emulos.o interrupts.o m68hc11_sim.o
22
 
23
# List of main object files for `run'.
24
SIM_RUN_OBJS = nrun.o
25
 
26
SIM_OBJS = $(M68HC11_OBJS) \
27
        $(SIM_NEW_COMMON_OBJS) \
28
        sim-load.o \
29
        sim-hload.o \
30
        sim-engine.o \
31
        sim-stop.o \
32
        sim-hrw.o \
33
        sim-reason.o \
34
        $(SIM_EXTRA_OBJS)
35
 
36
SIM_PROFILE= -DPROFILE=1 -DWITH_PROFILE=-1
37
# We must use 32-bit addresses to support memory bank switching.
38
# The WORD_BITSIZE is normally 16 but must be switched (temporarily)
39
# to 32 to avoid a bug in the sim-common which uses 'unsigned_word'
40
# instead of 'address_word' in some places (the result is a truncation
41
# of the 32-bit address to 16-bit; and this breaks the simulator).
42
SIM_EXTRA_CFLAGS = -DWITH_TARGET_WORD_BITSIZE=32 \
43
                   -DWITH_TARGET_CELL_BITSIZE=32 \
44
                   -DWITH_TARGET_ADDRESS_BITSIZE=32 \
45
                   -DWITH_TARGET_WORD_MSB=31
46
SIM_EXTRA_CLEAN = clean-extra
47
 
48
SIM_EXTRA_OBJS = @m68hc11_extra_objs@
49
 
50
INCLUDE = $(srcdir)/../../include/gdb/callback.h \
51
          interrupts.h sim-main.h
52
 
53
 
54
## COMMON_POST_CONFIG_FRAG
55
 
56
m68hc11int.c: gencode
57
        ./gencode -m6811 > $@
58
 
59
m68hc12int.c: gencode
60
        ./gencode -m6812 > $@
61
 
62
gencode:        gencode.c
63
        $(CC_FOR_BUILD) $(BUILD_CFLAGS) -o gencode $(srcdir)/gencode.c
64
 
65
interp.o: interp.c $(INCLUDE)
66
 
67
clean-extra:
68
        rm -f gencode m68hc11int.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.