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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [mips/] [m16.igen] - Blame information for rev 301

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1 24 jeremybenn
// -*- C -*-
2
//
3
//
4
// MIPS Architecture:
5
//
6
//        CPU Instruction Set (mips16)
7
//
8
 
9
// The instructions in this section are ordered according
10
// to http://www.sgi.com/MIPS/arch/MIPS16/mips16.pdf.
11
 
12
 
13
// The MIPS16 codes registers in a special way, map from one to the other.
14
// :::::::
15
:compute:::int:TRX:RX:((RX < 2) ? (16 + RX) \: RX)
16
:compute:::int:TRY:RY:((RY < 2) ? (16 + RY) \: RY)
17
:compute:::int:TRZ:RZ:((RZ < 2) ? (16 + RZ) \: RZ)
18
:compute:::int:SHIFT:SHAMT:((SHAMT == 0) ? 8 \: SHAMT)
19
 
20
:compute:::int:SHAMT:SHAMT_4_0,S5:(LSINSERTED (S5, 5, 5) | SHAMT_4_0)
21
 
22
:compute:::address_word:IMMEDIATE:IMM_25_21,IMM_20_16,IMMED_15_0:(LSINSERTED (IMM_25_21, 25, 21) | LSINSERTED (IMM_20_16, 20, 16) | LSINSERTED (IMMED_15_0, 15, 0))
23
:compute:::int:R32:R32L,R32H:((R32H << 3) | R32L)
24
 
25
:compute:::address_word:IMMEDIATE:IMM_10_5,IMM_15_11,IMM_4_0:(LSINSERTED (IMM_10_5, 10, 5) | LSINSERTED (IMM_15_11, 15, 11) | LSINSERTED (IMM_4_0, 4, 0))
26
 
27
:compute:::address_word:IMMEDIATE:IMM_10_4,IMM_14_11,IMM_3_0:(LSINSERTED (IMM_10_4, 10, 4) | LSINSERTED (IMM_14_11, 14, 11) | LSINSERTED (IMM_3_0, 3, 0))
28
 
29
 
30
// Load and Store Instructions
31
 
32
 
33
10000,3.RX,3.RY,5.IMMED:RRI:16::LB
34
"lb r,  (r)"
35
*mips16:
36
*vr4100:
37
{
38
  GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED));
39
}
40
 
41
11110,6.IMM_10_5,5.IMM_15_11 + 10000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LB
42
"lb r,  (r)"
43
*mips16:
44
*vr4100:
45
{
46
  GPR[TRY] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE)));
47
}
48
 
49
 
50
 
51
10100,3.RX,3.RY,5.IMMED:RRI:16::LBU
52
"lbu r,  (r)"
53
*mips16:
54
*vr4100:
55
{
56
  GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], IMMED);
57
}
58
 
59
11110,6.IMM_10_5,5.IMM_15_11 + 10100,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LBU
60
"lbu r,  (r)"
61
*mips16:
62
*vr4100:
63
{
64
  GPR[TRY] = do_load (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE));
65
}
66
 
67
 
68
 
69
10001,3.RX,3.RY,5.IMMED:RRI:16::LH
70
"lh r,  (r)"
71
*mips16:
72
*vr4100:
73
{
74
  GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1));
75
}
76
 
77
11110,6.IMM_10_5,5.IMM_15_11 + 10001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LH
78
"lh r,  (r)"
79
*mips16:
80
*vr4100:
81
{
82
  GPR[TRY] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
83
}
84
 
85
 
86
 
87
10101,3.RX,3.RY,5.IMMED:RRI:16::LHU
88
"lhu r,  (r)"
89
*mips16:
90
*vr4100:
91
{
92
  GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1);
93
}
94
 
95
11110,6.IMM_10_5,5.IMM_15_11 + 10101,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LHU
96
"lhu r,  (r)"
97
*mips16:
98
*vr4100:
99
{
100
  GPR[TRY] = do_load (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
101
}
102
 
103
 
104
 
105
10011,3.RX,3.RY,5.IMMED:RRI:16::LW
106
"lw r,  (r)"
107
*mips16:
108
*vr4100:
109
{
110
  GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2));
111
}
112
 
113
11110,6.IMM_10_5,5.IMM_15_11 + 10011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LW
114
"lw r,  (r)"
115
*mips16:
116
*vr4100:
117
{
118
  GPR[TRY] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE)));
119
}
120
 
121
 
122
 
123
10110,3.RX,8.IMMED:RI:16::LWPC
124
"lw r,  (PC)"
125
*mips16:
126
*vr4100:
127
{
128
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD,
129
                                basepc (SD_) & ~3, IMMED << 2));
130
}
131
 
132
11110,6.IMM_10_5,5.IMM_15_11 + 10110,3.RX,000,5.IMM_4_0:EXT-RI:16::LWPC
133
"lw r,  (PC)"
134
*mips16:
135
*vr4100:
136
{
137
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, basepc (SD_) & ~3, EXTEND16 (IMMEDIATE)));
138
}
139
 
140
 
141
 
142
10010,3.RX,8.IMMED:RI:16::LWSP
143
"lw r,  (SP)"
144
*mips16:
145
*vr4100:
146
{
147
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, IMMED << 2));
148
}
149
 
150
11110,6.IMM_10_5,5.IMM_15_11 + 10010,3.RX,000,5.IMM_4_0:EXT-RI:16::LWSP
151
"lw r,  (SP)"
152
*mips16:
153
*vr4100:
154
{
155
  GPR[TRX] = EXTEND32 (do_load (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE)));
156
}
157
 
158
 
159
 
160
10111,3.RX,3.RY,5.IMMED:RRI:16::LWU
161
"lwu r,  (r)"
162
*mips16:
163
*vr4100:
164
{
165
  GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2);
166
}
167
 
168
11110,6.IMM_10_5,5.IMM_15_11 + 10111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LWU
169
"lwu r,  (r)"
170
*mips16:
171
*vr4100:
172
{
173
  GPR[TRY] = do_load (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE));
174
}
175
 
176
 
177
 
178
00111,3.RX,3.RY,5.IMMED:RRI:16::LD
179
"ld r,  (r)"
180
*mips16:
181
*vr4100:
182
{
183
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3);
184
}
185
 
186
11110,6.IMM_10_5,5.IMM_15_11 + 00111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::LD
187
"ld r,  (r)"
188
*mips16:
189
*vr4100:
190
{
191
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE));
192
}
193
 
194
 
195
 
196
11111,100,3.RY,5.IMMED:RI64:16::LDPC
197
"ld r,  (PC)"
198
*mips16:
199
*vr4100:
200
{
201
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD,
202
                      basepc (SD_) & ~7, IMMED << 3);
203
}
204
 
205
11110,6.IMM_10_5,5.IMM_15_11 + 11111,100,3.RY,5.IMM_4_0:EXT-RI64:16::LDPC
206
"ld r,  (PC)"
207
*mips16:
208
*vr4100:
209
{
210
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, basepc (SD_) & ~7, EXTEND16 (IMMEDIATE));
211
}
212
 
213
 
214
 
215
11111,000,3.RY,5.IMMED:RI64:16::LDSP
216
"ld r,  (SP)"
217
*mips16:
218
*vr4100:
219
{
220
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3);
221
}
222
 
223
11110,6.IMM_10_5,5.IMM_15_11 + 11111,000,3.RY,5.IMM_4_0:EXT-RI64:16::LDSP
224
"ld r,  (SP)"
225
*mips16:
226
*vr4100:
227
{
228
  GPR[TRY] = do_load (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE));
229
}
230
 
231
 
232
 
233
11000,3.RX,3.RY,5.IMMED:RRI:16::SB
234
"sb r,  (r)"
235
*mips16:
236
*vr4100:
237
{
238
  do_store (SD_, AccessLength_BYTE, GPR[TRX], IMMED, GPR[TRY]);
239
}
240
 
241
11110,6.IMM_10_5,5.IMM_15_11 + 11000,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SB
242
"sb r,  (r)"
243
*mips16:
244
*vr4100:
245
{
246
  do_store (SD_, AccessLength_BYTE, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
247
}
248
 
249
 
250
 
251
11001,3.RX,3.RY,5.IMMED:RRI:16::SH
252
"sh r,  (r)"
253
*mips16:
254
*vr4100:
255
{
256
  do_store (SD_, AccessLength_HALFWORD, GPR[TRX], IMMED << 1, GPR[TRY]);
257
}
258
 
259
11110,6.IMM_10_5,5.IMM_15_11 + 11001,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SH
260
"sh r,  (r)"
261
*mips16:
262
*vr4100:
263
{
264
  do_store (SD_, AccessLength_HALFWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
265
}
266
 
267
 
268
 
269
11011,3.RX,3.RY,5.IMMED:RRI:16::SW
270
"sw r,  (r)"
271
*mips16:
272
*vr4100:
273
{
274
  do_store (SD_, AccessLength_WORD, GPR[TRX], IMMED << 2, GPR[TRY]);
275
}
276
 
277
11110,6.IMM_10_5,5.IMM_15_11 + 11011,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SW
278
"sw r,  (r)"
279
*mips16:
280
*vr4100:
281
{
282
  do_store (SD_, AccessLength_WORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
283
}
284
 
285
 
286
 
287
11010,3.RX,8.IMMED:RI:16::SWSP
288
"sw r,  (SP)"
289
*mips16:
290
*vr4100:
291
{
292
  do_store (SD_, AccessLength_WORD, SP, IMMED << 2, GPR[TRX]);
293
}
294
 
295
11110,6.IMM_10_5,5.IMM_15_11 + 11010,3.RX,000,5.IMM_4_0:EXT-RI:16::SWSP
296
"sw r,  (SP)"
297
*mips16:
298
*vr4100:
299
{
300
  do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), GPR[TRX]);
301
}
302
 
303
 
304
 
305
01100,010,8.IMMED:I8:16::SWRASP
306
"sw r,  (SP)"
307
*mips16:
308
*vr4100:
309
{
310
  do_store (SD_, AccessLength_WORD, SP, IMMED << 2, RA);
311
}
312
 
313
11110,6.IMM_10_5,5.IMM_15_11 + 01100,010,000,5.IMM_4_0:EXT-I8:16::SWRASP
314
"sw r,  (SP)"
315
*mips16:
316
*vr4100:
317
{
318
  do_store (SD_, AccessLength_WORD, SP, EXTEND16 (IMMEDIATE), RA);
319
}
320
 
321
 
322
 
323
01111,3.RX,3.RY,5.IMMED:RRI:16::SD
324
"sd r,  (r)"
325
*mips16:
326
*vr4100:
327
{
328
  do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], IMMED << 3, GPR[TRY]);
329
}
330
 
331
11110,6.IMM_10_5,5.IMM_15_11 + 01111,3.RX,3.RY,5.IMM_4_0:EXT-RRI:16::SD
332
"sd r,  (r)"
333
*mips16:
334
*vr4100:
335
{
336
  do_store (SD_, AccessLength_DOUBLEWORD, GPR[TRX], EXTEND16 (IMMEDIATE), GPR[TRY]);
337
}
338
 
339
 
340
 
341
11111,001,3.RY,5.IMMED:RI64:16::SDSP
342
"sd r,  (SP)"
343
*mips16:
344
*vr4100:
345
{
346
  do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, GPR[TRY]);
347
}
348
 
349
11110,6.IMM_10_5,5.IMM_15_11 + 11111,001,3.RY,5.IMM_4_0:EXT-RI64:16::SDSP
350
"sd r,  (SP)"
351
*mips16:
352
*vr4100:
353
{
354
  do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), GPR[TRY]);
355
}
356
 
357
 
358
 
359
11111,010,8.IMMED:I64:16::SDRASP
360
"sd r,  (SP)"
361
*mips16:
362
*vr4100:
363
{
364
  do_store (SD_, AccessLength_DOUBLEWORD, SP, IMMED << 3, RA);
365
}
366
 
367
11110,6.IMM_10_5,5.IMM_15_11 + 11111,010,000,5.IMM_4_0:EXT-I64:16::SDRASP
368
"sd r,  (SP)"
369
*mips16:
370
*vr4100:
371
{
372
  do_store (SD_, AccessLength_DOUBLEWORD, SP, EXTEND16 (IMMEDIATE), RA);
373
}
374
 
375
 
376
 
377
// ALU Immediate Instructions
378
 
379
 
380
01101,3.RX,8.IMMED:RI:16::LI
381
"li r, "
382
*mips16:
383
*vr4100:
384
{
385
  do_ori (SD_, 0, TRX, IMMED);
386
}
387
 
388
11110,6.IMM_10_5,5.IMM_15_11 + 01101,3.RX,000,5.IMM_4_0:EXT-RI:16::LI
389
"li r, "
390
*mips16:
391
*vr4100:
392
{
393
  do_ori (SD_, 0, TRX, IMMEDIATE);
394
}
395
 
396
 
397
 
398
01000,3.RX,3.RY,0,4.IMMED:RRI-A:16::ADDIU
399
"addiu r, r, "
400
*mips16:
401
*vr4100:
402
{
403
  do_addiu (SD_, TRX, TRY, EXTEND4 (IMMED));
404
}
405
 
406
11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,0,4.IMM_3_0:EXT-RRI-A:16::ADDIU
407
"addiu r, r, "
408
*mips16:
409
*vr4100:
410
{
411
  do_addiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
412
}
413
 
414
 
415
 
416
01001,3.RX,8.IMMED:RI:16::ADDIU8
417
"addiu r, "
418
*mips16:
419
*vr4100:
420
{
421
  do_addiu (SD_, TRX, TRX, EXTEND8 (IMMED));
422
}
423
 
424
11110,6.IMM_10_5,5.IMM_15_11 + 01001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIU8
425
"addiu r, "
426
*mips16:
427
*vr4100:
428
{
429
  do_addiu (SD_, TRX, TRX, EXTEND16 (IMMEDIATE));
430
}
431
 
432
 
433
 
434
01100,011,8.IMMED:I8:16::ADJSP
435
"addiu SP, "
436
*mips16:
437
*vr4100:
438
{
439
  do_addiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
440
}
441
 
442
11110,6.IMM_10_5,5.IMM_15_11 + 01100,011,000,5.IMM_4_0:EXT-I8:16::ADJSP
443
"addiu SP, "
444
*mips16:
445
*vr4100:
446
{
447
  do_addiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
448
}
449
 
450
 
451
 
452
00001,3.RX,8.IMMED:RI:16::ADDIUPC
453
"addiu r, PC, "
454
*mips16:
455
*vr4100:
456
{
457
  unsigned32 temp = (basepc (SD_) & ~3) + (IMMED << 2);
458
  GPR[TRX] = EXTEND32 (temp);
459
}
460
 
461
11110,6.IMM_10_5,5.IMM_15_11 + 00001,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUPC
462
"addiu r, PC, "
463
*mips16:
464
*vr4100:
465
{
466
  unsigned32 temp = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
467
  GPR[TRX] = EXTEND32 (temp);
468
}
469
 
470
 
471
 
472
00000,3.RX,8.IMMED:RI:16::ADDIUSP
473
"addiu r, SP, "
474
*mips16:
475
*vr4100:
476
{
477
  do_addiu (SD_, SPIDX, TRX, IMMED << 2);
478
}
479
 
480
11110,6.IMM_10_5,5.IMM_15_11 + 00000,3.RX,000,5.IMM_4_0:EXT-RI:16::ADDIUSP
481
"addiu r, SP, "
482
*mips16:
483
*vr4100:
484
{
485
  do_addiu (SD_, SPIDX, TRX, EXTEND16 (IMMEDIATE));
486
}
487
 
488
 
489
 
490
01000,3.RX,3.RY,1,4.IMMED:RRI-A:16::DADDIU
491
"daddiu r, r, "
492
*mips16:
493
*vr4100:
494
{
495
  do_daddiu (SD_, TRX, TRY, EXTEND4 (IMMED));
496
}
497
 
498
11110,7.IMM_10_4,4.IMM_14_11 + 01000,3.RX,3.RY,1,4.IMM_3_0:EXT-RRI-A:16::DADDIU
499
"daddiu r, r, "
500
*mips16:
501
*vr4100:
502
{
503
  do_daddiu (SD_, TRX, TRY, EXTEND15 (IMMEDIATE));
504
}
505
 
506
 
507
 
508
11111,101,3.RY,5.IMMED:RI64:16::DADDIU5
509
"daddiu r, "
510
*mips16:
511
*vr4100:
512
{
513
  do_daddiu (SD_, TRY, TRY, EXTEND5 (IMMED));
514
}
515
 
516
11110,6.IMM_10_5,5.IMM_15_11 + 11111,101,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIU5
517
"daddiu r, "
518
*mips16:
519
*vr4100:
520
{
521
  do_daddiu (SD_, TRY, TRY, EXTEND16 (IMMEDIATE));
522
}
523
 
524
 
525
 
526
11111,011,8.IMMED:I64:16::DADJSP
527
"daddiu SP, "
528
*mips16:
529
*vr4100:
530
{
531
  do_daddiu (SD_, SPIDX, SPIDX, EXTEND8 (IMMED) << 3);
532
}
533
 
534
11110,6.IMM_10_5,5.IMM_15_11 + 11111,011,000,5.IMM_4_0:EXT-I64:16::DADJSP
535
"daddiu SP, "
536
*mips16:
537
*vr4100:
538
{
539
  do_daddiu (SD_, SPIDX, SPIDX, EXTEND16 (IMMEDIATE));
540
}
541
 
542
 
543
 
544
11111,110,3.RY,5.IMMED:RI64:16::DADDIUPC
545
"daddiu r, PC, "
546
*mips16:
547
*vr4100:
548
{
549
  GPR[TRY] = (basepc (SD_) & ~3) + (IMMED << 2);
550
}
551
 
552
11110,6.IMM_10_5,5.IMM_15_11 + 11111,110,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUPC
553
"daddiu r, PC, "
554
*mips16:
555
*vr4100:
556
{
557
  GPR[TRY] = (basepc (SD_) & ~3) + EXTEND16 (IMMEDIATE);
558
}
559
 
560
 
561
 
562
11111,111,3.RY,5.IMMED:RI64:16::DADDIUSP
563
"daddiu r, SP, "
564
*mips16:
565
*vr4100:
566
{
567
  do_daddiu (SD_, SPIDX, TRY, IMMED << 2);
568
}
569
 
570
11110,6.IMM_10_5,5.IMM_15_11 + 11111,111,3.RY,5.IMM_4_0:EXT-RI64:16::DADDIUSP
571
"daddiu r, SP, "
572
*mips16:
573
*vr4100:
574
{
575
  do_daddiu (SD_, SPIDX, TRY, EXTEND16 (IMMEDIATE));
576
}
577
 
578
 
579
 
580
01010,3.RX,8.IMMED:RI:16::SLTI
581
"slti r, "
582
*mips16:
583
*vr4100:
584
{
585
  do_slti (SD_, TRX, T8IDX, IMMED);
586
}
587
 
588
11110,6.IMM_10_5,5.IMM_15_11 + 01010,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTI
589
"slti r, "
590
*mips16:
591
*vr4100:
592
{
593
  do_slti (SD_, TRX, T8IDX, IMMEDIATE);
594
}
595
 
596
 
597
 
598
01011,3.RX,8.IMMED:RI:16::SLTIU
599
"sltiu r, "
600
*mips16:
601
*vr4100:
602
{
603
  do_sltiu (SD_, TRX, T8IDX, IMMED);
604
}
605
 
606
11110,6.IMM_10_5,5.IMM_15_11 + 01011,3.RX,000,5.IMM_4_0:EXT-RI:16::SLTIU
607
"sltiu r, "
608
*mips16:
609
*vr4100:
610
{
611
  do_sltiu (SD_, TRX, T8IDX, IMMEDIATE);
612
}
613
 
614
 
615
 
616
11101,3.RX,3.RY,01010:RR:16::CMP
617
"cmp r, r"
618
*mips16:
619
*vr4100:
620
{
621
  do_xor (SD_, TRX, TRY, T8IDX);
622
}
623
 
624
 
625
01110,3.RX,8.IMMED:RI:16::CMPI
626
"cmpi r, "
627
*mips16:
628
*vr4100:
629
{
630
  do_xori (SD_, TRX, T8IDX, IMMED);
631
}
632
 
633
11110,6.IMM_10_5,5.IMM_15_11 + 01110,3.RX,000,5.IMM_4_0:EXT-RI:16::CMPI
634
"sltiu r, "
635
*mips16:
636
*vr4100:
637
{
638
  do_xori (SD_, TRX, T8IDX, IMMEDIATE);
639
}
640
 
641
 
642
 
643
// Two/Three Operand, Register-Type
644
 
645
 
646
 
647
11100,3.RX,3.RY,3.RZ,01:RRR:16::ADDU
648
"addu r, r, r"
649
*mips16:
650
*vr4100:
651
{
652
  do_addu (SD_, TRX, TRY, TRZ);
653
}
654
 
655
 
656
 
657
11100,3.RX,3.RY,3.RZ,11:RRR:16::SUBU
658
"subu r, r, r"
659
*mips16:
660
*vr4100:
661
{
662
  do_subu (SD_, TRX, TRY, TRZ);
663
}
664
 
665
11100,3.RX,3.RY,3.RZ,00:RRR:16::DADDU
666
"daddu r, r, r"
667
*mips16:
668
*vr4100:
669
{
670
  do_daddu (SD_, TRX, TRY, TRZ);
671
}
672
 
673
 
674
 
675
11100,3.RX,3.RY,3.RZ,10:RRR:16::DSUBU
676
"dsubu r, r, r"
677
*mips16:
678
*vr4100:
679
{
680
  do_dsubu (SD_, TRX, TRY, TRZ);
681
}
682
 
683
 
684
 
685
11101,3.RX,3.RY,00010:RR:16::SLT
686
"slt r, r"
687
*mips16:
688
*vr4100:
689
{
690
  do_slt (SD_, TRX, TRY, T8IDX);
691
}
692
 
693
 
694
 
695
11101,3.RX,3.RY,00011:RR:16::SLTU
696
"sltu r, r"
697
*mips16:
698
*vr4100:
699
{
700
  do_sltu (SD_, TRX, TRY, T8IDX);
701
}
702
 
703
 
704
 
705
11101,3.RX,3.RY,01011:RR:16::NEG
706
"neg r, r"
707
*mips16:
708
*vr4100:
709
{
710
  do_subu (SD_, 0, TRY, TRX);
711
}
712
 
713
 
714
 
715
11101,3.RX,3.RY,01100:RR:16::AND
716
"and r, r"
717
*mips16:
718
*vr4100:
719
{
720
  do_and (SD_, TRX, TRY, TRX);
721
}
722
 
723
 
724
 
725
11101,3.RX,3.RY,01101:RR:16::OR
726
"or r, r"
727
*mips16:
728
*vr4100:
729
{
730
  do_or (SD_, TRX, TRY, TRX);
731
}
732
 
733
 
734
 
735
11101,3.RX,3.RY,01110:RR:16::XOR
736
"xor r, r"
737
*mips16:
738
*vr4100:
739
{
740
  do_xor (SD_, TRX, TRY, TRX);
741
}
742
 
743
 
744
 
745
11101,3.RX,3.RY,01111:RR:16::NOT
746
"not r, r"
747
*mips16:
748
*vr4100:
749
{
750
  do_nor (SD_, 0, TRY, TRX);
751
}
752
 
753
 
754
 
755
01100,111,3.RY,5.R32:I8_MOVR32:16::MOVR32
756
"move r, r"
757
*mips16:
758
*vr4100:
759
{
760
  do_or (SD_, R32, 0, TRY);
761
}
762
 
763
 
764
 
765
01100,101,3.R32L,2.R32H,3.RZ:I8_MOV32R:16::MOV32R
766
"move r, r"
767
*mips16:
768
*vr4100:
769
{
770
  do_or (SD_, TRZ, 0, R32);
771
}
772
 
773
 
774
 
775
00110,3.RX,3.RY,3.SHAMT,00:SHIFT:16::SLL
776
"sll r, r, "
777
*mips16:
778
*vr4100:
779
{
780
  do_sll (SD_, TRY, TRX, SHIFT);
781
}
782
 
783
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,00:EXT-SHIFT:16::SLL
784
"sll r, r, "
785
*mips16:
786
*vr4100:
787
{
788
  do_sll (SD_, TRY, TRX, SHAMT);
789
}
790
 
791
 
792
 
793
00110,3.RX,3.RY,3.SHAMT,10:SHIFT:16::SRL
794
"srl r, r, "
795
*mips16:
796
*vr4100:
797
{
798
  do_srl (SD_, TRY, TRX, SHIFT);
799
}
800
 
801
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,10:EXT-SHIFT:16::SRL
802
"srl r, r, "
803
*mips16:
804
*vr4100:
805
{
806
  do_srl (SD_, TRY, TRX, SHAMT);
807
}
808
 
809
 
810
 
811
00110,3.RX,3.RY,3.SHAMT,11:SHIFT:16::SRA
812
"sra r, r, "
813
*mips16:
814
*vr4100:
815
{
816
  do_sra (SD_, TRY, TRX, SHIFT);
817
}
818
 
819
11110,5.SHAMT,0,00000 + 00110,3.RX,3.RY,000,11:EXT-SHIFT:16::SRA
820
"sra r, r, "
821
*mips16:
822
*vr4100:
823
{
824
  do_sra (SD_, TRY, TRX, SHAMT);
825
}
826
 
827
 
828
 
829
11101,3.RX,3.RY,00100:RR:16::SLLV
830
"sllv r, r"
831
*mips16:
832
*vr4100:
833
{
834
  do_sllv (SD_, TRX, TRY, TRY);
835
}
836
 
837
 
838
11101,3.RX,3.RY,00110:RR:16::SRLV
839
"srlv r, r"
840
*mips16:
841
*vr4100:
842
{
843
  do_srlv (SD_, TRX, TRY, TRY);
844
}
845
 
846
 
847
11101,3.RX,3.RY,00111:RR:16::SRAV
848
"srav r, r"
849
*mips16:
850
*vr4100:
851
{
852
  do_srav (SD_, TRX, TRY, TRY);
853
}
854
 
855
 
856
00110,3.RX,3.RY,3.SHAMT,01:SHIFT:16::DSLL
857
"dsll r, r, "
858
*mips16:
859
*vr4100:
860
{
861
  do_dsll (SD_, TRY, TRX, SHIFT);
862
}
863
 
864
11110,5.SHAMT_4_0,1.S5,00000 + 00110,3.RX,3.RY,000,01:EXT-SHIFT:16::DSLL
865
"dsll r, r, "
866
*mips16:
867
*vr4100:
868
{
869
  do_dsll (SD_, TRY, TRX, SHAMT);
870
}
871
 
872
 
873
 
874
11101,3.SHAMT,3.RY,01000:SHIFT64:16::DSRL
875
"dsrl r, "
876
*mips16:
877
*vr4100:
878
{
879
  do_dsrl (SD_, TRY, TRY, SHIFT);
880
}
881
 
882
11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,01000:EXT-SHIFT64:16::DSRL
883
"dsrl r, "
884
*mips16:
885
*vr4100:
886
{
887
  do_dsrl (SD_, TRY, TRY, SHAMT);
888
}
889
 
890
 
891
 
892
11101,3.SHAMT,3.RY,10011:SHIFT64:16::DSRA
893
"dsra r, "
894
*mips16:
895
*vr4100:
896
{
897
  do_dsra (SD_, TRY, TRY, SHIFT);
898
}
899
 
900
11110,5.SHAMT_4_0,1.S5,00000 + 11101,000,3.RY,10011:EXT-SHIFT64:16::DSRA
901
"dsra r, "
902
*mips16:
903
*vr4100:
904
{
905
  do_dsra (SD_, TRY, TRY, SHAMT);
906
}
907
 
908
 
909
 
910
11101,3.RX,3.RY,10100:RR:16::DSLLV
911
"dsllv r, r"
912
*mips16:
913
*vr4100:
914
{
915
  do_dsllv (SD_, TRX, TRY, TRY);
916
}
917
 
918
 
919
11101,3.RX,3.RY,10110:RR:16::DSRLV
920
"dsrlv r, r"
921
*mips16:
922
*vr4100:
923
{
924
  do_dsrlv (SD_, TRX, TRY, TRY);
925
}
926
 
927
 
928
11101,3.RX,3.RY,10111:RR:16::DSRAV
929
"dsrav r, r"
930
*mips16:
931
*vr4100:
932
{
933
  do_dsrav (SD_, TRX, TRY, TRY);
934
}
935
 
936
 
937
// Multiply /Divide Instructions
938
 
939
 
940
11101,3.RX,3.RY,11000:RR:16::MULT
941
"mult r, r"
942
*mips16:
943
*vr4100:
944
{
945
  do_mult (SD_, TRX, TRY, 0);
946
}
947
 
948
 
949
11101,3.RX,3.RY,11001:RR:16::MULTU
950
"multu r, r"
951
*mips16:
952
*vr4100:
953
{
954
  do_multu (SD_, TRX, TRY, 0);
955
}
956
 
957
 
958
11101,3.RX,3.RY,11010:RR:16::DIV
959
"div r, r"
960
*mips16:
961
*vr4100:
962
{
963
  do_div (SD_, TRX, TRY);
964
}
965
 
966
 
967
11101,3.RX,3.RY,11011:RR:16::DIVU
968
"divu r, r"
969
*mips16:
970
*vr4100:
971
{
972
  do_divu (SD_, TRX, TRY);
973
}
974
 
975
 
976
11101,3.RX,000,10000:RR:16::MFHI
977
"mfhi r"
978
*mips16:
979
*vr4100:
980
{
981
  do_mfhi (SD_, TRX);
982
}
983
 
984
 
985
11101,3.RX,000,10010:RR:16::MFLO
986
"mflo r"
987
*mips16:
988
*vr4100:
989
{
990
  do_mflo (SD_, TRX);
991
}
992
 
993
 
994
11101,3.RX,3.RY,11100:RR:16::DMULT
995
"dmult r, r"
996
*mips16:
997
*vr4100:
998
{
999
  do_dmult (SD_, TRX, TRY, 0);
1000
}
1001
 
1002
 
1003
11101,3.RX,3.RY,11101:RR:16::DMULTU
1004
"dmultu r, r"
1005
*mips16:
1006
*vr4100:
1007
{
1008
  do_dmultu (SD_, TRX, TRY, 0);
1009
}
1010
 
1011
 
1012
11101,3.RX,3.RY,11110:RR:16::DDIV
1013
"ddiv r, r"
1014
*mips16:
1015
*vr4100:
1016
{
1017
  do_ddiv (SD_, TRX, TRY);
1018
}
1019
 
1020
 
1021
11101,3.RX,3.RY,11111:RR:16::DDIVU
1022
"ddivu r, r"
1023
*mips16:
1024
*vr4100:
1025
{
1026
  do_ddivu (SD_, TRX, TRY);
1027
}
1028
 
1029
 
1030
// Jump and Branch Instructions
1031
 
1032
 
1033
 
1034
// Issue instruction in delay slot of branch
1035
:function:::address_word:delayslot16:address_word nia, address_word target
1036
{
1037
  instruction_word delay_insn;
1038
  sim_events_slip (SD, 1);
1039
  DSPC = CIA; /* save current PC somewhere */
1040
  STATE |= simDELAYSLOT;
1041
  delay_insn = IMEM16 (nia); /* NOTE: mips16 */
1042
  idecode_issue (CPU_, delay_insn, (nia));
1043
  STATE &= ~simDELAYSLOT;
1044
  return target;
1045
}
1046
 
1047
// compute basepc dependant on us being in a delay slot
1048
:function:::address_word:basepc:
1049
{
1050
  if (STATE & simDELAYSLOT)
1051
    {
1052
      return DSPC; /* return saved address of preceeding jmp */
1053
    }
1054
  else
1055
    {
1056
      return CIA;
1057
    }
1058
}
1059
 
1060
 
1061
// JAL
1062
00011,0,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JAL:16::JAL
1063
"jal "
1064
*mips16:
1065
*vr4100:
1066
{
1067
  address_word region = (NIA & MASK (63, 28));
1068
  RA = NIA + 2; /* skip 16 bit delayslot insn */
1069
  NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2))) | 1;
1070
}
1071
 
1072
 
1073
 
1074
// JALX - 32 and 16 bit versions.
1075
 
1076
011101,26.IMMED:JALX:32::JALX32
1077
"jalx "
1078
*mips16:
1079
*vr4100:
1080
{
1081
  address_word region = (NIA & MASK (63, 28));
1082
  RA = NIA + 4; /* skip 32 bit delayslot insn */
1083
  NIA = delayslot32 (SD_, (region | (IMMED << 2)) | 1);
1084
}
1085
 
1086
00011,1,5.IMM_20_16,5.IMM_25_21 + 16.IMMED_15_0:JALX:16::JALX16
1087
"jalx "
1088
*mips16:
1089
*vr4100:
1090
{
1091
  address_word region = (NIA & MASK (63, 28));
1092
  RA = NIA + 2; /* 16 bit INSN */
1093
  NIA = delayslot16 (SD_, NIA, (region | (IMMEDIATE << 2)) & ~1);
1094
}
1095
 
1096
 
1097
 
1098
11101,3.RX,000,00000:RR:16::JR
1099
"jr r"
1100
*mips16:
1101
*vr4100:
1102
{
1103
  NIA = delayslot16 (SD_, NIA, GPR[TRX]);
1104
}
1105
 
1106
 
1107
11101,000,001,00000:RR:16::JRRA
1108
"jrra"
1109
*mips16:
1110
*vr4100:
1111
{
1112
  NIA = delayslot16 (SD_, NIA, RA);
1113
}
1114
 
1115
 
1116
 
1117
11101,3.RX,010,00000:RR:16::JALR
1118
"jalr r"
1119
*mips16:
1120
*vr4100:
1121
{
1122
  RA = NIA + 2;
1123
  NIA = delayslot16 (SD_, NIA, GPR[TRX]);
1124
}
1125
 
1126
 
1127
 
1128
00100,3.RX,8.IMMED:RI:16::BEQZ
1129
"beqz r, "
1130
*mips16:
1131
*vr4100:
1132
{
1133
  if (GPR[TRX] == 0)
1134
    NIA = (NIA + (EXTEND8 (IMMED) << 1));
1135
}
1136
 
1137
11110,6.IMM_10_5,5.IMM_15_11 + 00100,3.RX,000,5.IMM_4_0:EXT-RI:16::BEQZ
1138
"beqz r, "
1139
*mips16:
1140
*vr4100:
1141
{
1142
  if (GPR[TRX] == 0)
1143
    NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
1144
}
1145
 
1146
 
1147
 
1148
00101,3.RX,8.IMMED:RI:16::BNEZ
1149
"bnez r, "
1150
*mips16:
1151
*vr4100:
1152
{
1153
  if (GPR[TRX] != 0)
1154
    NIA = (NIA + (EXTEND8 (IMMED) << 1));
1155
}
1156
 
1157
11110,6.IMM_10_5,5.IMM_15_11 + 00101,3.RX,000,5.IMM_4_0:EXT-RI:16::BNEZ
1158
"bnez r, "
1159
*mips16:
1160
*vr4100:
1161
{
1162
  if (GPR[TRX] != 0)
1163
    NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
1164
}
1165
 
1166
 
1167
 
1168
01100,000,8.IMMED:I8:16::BTEQZ
1169
"bteqz "
1170
*mips16:
1171
*vr4100:
1172
{
1173
  if (T8 == 0)
1174
    NIA = (NIA + (EXTEND8 (IMMED) << 1));
1175
}
1176
 
1177
11110,6.IMM_10_5,5.IMM_15_11 + 01100,000,000,5.IMM_4_0:EXT-I8:16::BTEQZ
1178
"bteqz "
1179
*mips16:
1180
*vr4100:
1181
{
1182
  if (T8 == 0)
1183
    NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
1184
}
1185
 
1186
 
1187
 
1188
01100,001,8.IMMED:I8:16::BTNEZ
1189
"btnez "
1190
*mips16:
1191
*vr4100:
1192
{
1193
  if (T8 != 0)
1194
    NIA = (NIA + (EXTEND8 (IMMED) << 1));
1195
}
1196
 
1197
11110,6.IMM_10_5,5.IMM_15_11 + 01100,001,000,5.IMM_4_0:EXT-I8:16::BTNEZ
1198
"btnez "
1199
*mips16:
1200
*vr4100:
1201
{
1202
  if (T8 != 0)
1203
    NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
1204
}
1205
 
1206
 
1207
 
1208
00010,11.IMMED:I:16::B
1209
"b "
1210
*mips16:
1211
*vr4100:
1212
{
1213
  NIA = (NIA + (EXTEND11 (IMMED) << 1));
1214
}
1215
 
1216
11110,6.IMM_10_5,5.IMM_15_11 + 00010,6.0,5.IMM_4_0:EXT-I:16::B
1217
"b "
1218
*mips16:
1219
*vr4100:
1220
{
1221
  NIA = (NIA + (EXTEND16 (IMMEDIATE) << 1));
1222
}
1223
 
1224
 
1225
 
1226
11101,3.RX,3.RY,00101:RR:16::BREAK
1227
"break"
1228
*mips16:
1229
*vr4100:
1230
{
1231
  if (STATE & simDELAYSLOT)
1232
    PC = cia - 2; /* reference the branch instruction */
1233
  else
1234
    PC = cia;
1235
  SignalException (BreakPoint, instruction_0);
1236
}

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