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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [mips/] [mips3264r2.igen] - Blame information for rev 310

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1 24 jeremybenn 
// -*- C -*-
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// Simulator definition for the MIPS 32/64 revision 2 instructions.
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// Copyright (C) 2004 Free Software Foundation, Inc.
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// Contributed by David Ung, of MIPS Technologies.
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//
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// This file is part of GDB, the GNU debugger.
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//
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// This program is free software; you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation; either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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011111,5.RS,5.RT,5.SIZE,5.LSB,000011::64::DEXT
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"dext r, r, , "
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*mips64r2:
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{
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  check_u64 (SD_, instruction_0);
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  TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
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  GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE, LSB);
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  TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.SIZE,5.LSB,000001::64::DEXTM
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"dextm r, r, , "
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*mips64r2:
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{
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  check_u64 (SD_, instruction_0);
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  TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
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  GPR[RT] = EXTRACTED64 (GPR[RS], LSB + SIZE + 32, LSB);
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  TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.SIZE,5.LSB,000010::64::DEXTU
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"dextu r, r, , "
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*mips64r2:
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{
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  check_u64 (SD_, instruction_0);
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  TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
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  GPR[RT] = EXTRACTED64 (GPR[RS], LSB + 32 + SIZE, LSB + 32);
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  TRACE_ALU_RESULT1 (GPR[RT]);
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}
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53 
 
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010000,01011,5.RT,01100,00000,0,00,000::32::DI
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"di":RT == 0
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"di r"
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*mips32r2:
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*mips64r2:
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{
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  TRACE_ALU_INPUT0 ();
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  GPR[RT] = EXTEND32 (SR);
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  SR &= ~status_IE;
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  TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.MSB,5.LSB,000111::64::DINS
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"dins r, r, , "
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*mips64r2:
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{
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  check_u64 (SD_, instruction_0);
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  TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
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  if (LSB <= MSB)
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    GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB, LSB);
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  TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.MSB,5.LSB,000101::64::DINSM
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"dinsm r, r, , "
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*mips64r2:
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{
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  check_u64 (SD_, instruction_0);
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  TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
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  if (LSB <= MSB + 32)
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    GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << LSB)) & MASK64 (MSB + 32, LSB);
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  TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.MSB,5.LSB,000110::64::DINSU
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"dinsu r, r, , "
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*mips64r2:
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{
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  check_u64 (SD_, instruction_0);
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  TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
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  if (LSB <= MSB)
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    GPR[RT] ^= (GPR[RT] ^ (GPR[RS] << (LSB + 32)))
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      & MASK64 (MSB + 32, LSB + 32);
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  TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,00000,5.RT,5.RD,00010,100100::64::DSBH
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"dsbh r, r"
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*mips64r2:
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{
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  union { unsigned64 d; unsigned16 h[4]; } u;
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  check_u64 (SD_, instruction_0);
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  TRACE_ALU_INPUT1 (GPR[RT]);
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  u.d = GPR[RT];
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  u.h[0] = SWAP_2 (u.h[0]);
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  u.h[1] = SWAP_2 (u.h[1]);
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  u.h[2] = SWAP_2 (u.h[2]);
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  u.h[3] = SWAP_2 (u.h[3]);
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  GPR[RD] = u.d;
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  TRACE_ALU_RESULT1 (GPR[RD]);
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}
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011111,00000,5.RT,5.RD,00101,100100::64::DSHD
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"dshd r, r"
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*mips64r2:
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{
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  unsigned64 d;
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  check_u64 (SD_, instruction_0);
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  TRACE_ALU_INPUT1 (GPR[RT]);
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  d = GPR[RT];
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  GPR[RD] = ((d >> 48)
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             | (d << 48)
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             | ((d & 0x0000ffff00000000ULL) >> 16)
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             | ((d & 0x00000000ffff0000ULL) << 16));
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  TRACE_ALU_RESULT1 (GPR[RD]);
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}
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010000,01011,5.RT,01100,00000,1,00,000::32::EI
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"ei":RT == 0
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"ei r"
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*mips32r2:
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*mips64r2:
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{
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  TRACE_ALU_INPUT0 ();
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  GPR[RT] = EXTEND32 (SR);
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  SR |= status_IE;
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  TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,5.RS,5.RT,5.SIZE,5.LSB,000000::32::EXT
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"ext r, r, , "
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*mips32r2:
150 
*mips64r2:
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{
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  TRACE_ALU_INPUT3 (GPR[RS], LSB, SIZE);
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  GPR[RT] = EXTEND32 (EXTRACTED32 (GPR[RS], LSB + SIZE, LSB));
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  TRACE_ALU_RESULT1 (GPR[RT]);
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}
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158 
010001,00011,5.RT,5.FS,00000000000:COP1Sa:32,f::MFHC1
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"mfhc1 r, f"
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*mips32r2:
161 
*mips64r2:
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{
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  check_fpu (SD_);
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  if (SizeFGR() == 64)
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    GPR[RT] = EXTEND32 (WORD64HI (FGR[FS]));
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  else if ((FS & 0x1) == 0)
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    GPR[RT] = EXTEND32 (FGR[FS + 1]);
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  else
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    {
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      if (STATE_VERBOSE_P(SD))
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        sim_io_eprintf (SD,
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                 "Warning: PC 0x%lx: MFHC1 32-bit use of odd FPR number\n",
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                        (long) CIA);
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      GPR[RT] = EXTEND32 (0xBADF00D);
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    }
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  TRACE_ALU_RESULT (GPR[RT]);
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}
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010001,00111,5.RT,5.FS,00000000000:COP1Sa:32,f::MTHC1
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"mthc1 r, f"
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*mips32r2:
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*mips64r2:
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{
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  check_fpu (SD_);
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  if (SizeFGR() == 64)
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    StoreFPR (FS, fmt_uninterpreted_64, SET64HI (GPR[RT]) | VL4_8 (FGR[FS]));
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  else if ((FS & 0x1) == 0)
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    StoreFPR (FS + 1, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
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  else
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    {
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      if (STATE_VERBOSE_P(SD))
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        sim_io_eprintf (SD,
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                 "Warning: PC 0x%lx: MTHC1 32-bit use of odd FPR number\n",
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                        (long) CIA);
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      StoreFPR (FS, fmt_uninterpreted_32, 0xDEADC0DE);
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    }
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  TRACE_FP_RESULT (GPR[RT]);
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}
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201 
011111,5.RS,5.RT,5.MSB,5.LSB,000100::32::INS
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"ins r, r, , "
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*mips32r2:
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*mips64r2:
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{
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  TRACE_ALU_INPUT4 (GPR[RT], GPR[RS], LSB, MSB);
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  if (LSB <= MSB)
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    GPR[RT] = EXTEND32 (GPR[RT] ^
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                        ((GPR[RT] ^ (GPR[RS] << LSB)) & MASK32 (MSB, LSB)));
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  TRACE_ALU_RESULT1 (GPR[RT]);
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}
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011111,00000,5.RT,5.RD,10000,100000::32::SEB
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"seb r, r"
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*mips32r2:
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*mips64r2:
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{
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  TRACE_ALU_INPUT1 (GPR[RT]);
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  GPR[RD] = EXTEND8 (GPR[RT]);
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  TRACE_ALU_RESULT1 (GPR[RD]);
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}
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011111,00000,5.RT,5.RD,11000,100000::32::SEH
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"seh r, r"
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*mips32r2:
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*mips64r2:
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{
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  TRACE_ALU_INPUT1 (GPR[RT]);
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  GPR[RD] = EXTEND16 (GPR[RT]);
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  TRACE_ALU_RESULT1 (GPR[RD]);
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}
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234 
 
235 
000001,5.BASE,11111,16.OFFSET::32::SYNCI
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"synci (r)"
237 
*mips32r2:
238 
*mips64r2:
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{
240 
  // sync i-cache - nothing to do currently
241 
}
242 
 
243 
 
244 
011111,00000,5.RT,5.RD,00010,100000::32::WSBH
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"wsbh r, r"
246 
*mips32r2:
247 
*mips64r2:
248 
{
249 
  union { unsigned32 w; unsigned16 h[2]; } u;
250 
  TRACE_ALU_INPUT1 (GPR[RT]);
251 
  u.w = GPR[RT];
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  u.h[0] = SWAP_2 (u.h[0]);
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  u.h[1] = SWAP_2 (u.h[1]);
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  GPR[RD] = EXTEND32 (u.w);
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  TRACE_ALU_RESULT1 (GPR[RD]);
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}
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