OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [or32/] [or32sim.h] - Blame information for rev 621

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 147 jeremybenn
/* Header for GDB Simulator wrapper for Or1ksim
2
 
3
   Copyright 1988-2008, Free Software Foundation, Inc.
4
   Copyright (C) 2010 Embecosm Limited
5
 
6
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
7
 
8
   This file is part of GDB.
9
 
10
   This program is free software; you can redistribute it and/or modify it
11
   under the terms of the GNU General Public License as published by the Free
12
   Software Foundation; either version 3 of the License, or (at your option)
13
   any later version.
14
 
15
   This program is distributed in the hope that it will be useful, but WITHOUT
16
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
18
   more details.
19
 
20
   You should have received a copy of the GNU General Public License along
21
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
22
 
23
/*---------------------------------------------------------------------------*/
24
/* This is a wrapper for Or1ksim, suitable for use as a GDB simulator.
25
 
26
   The code tries to follow the GDB coding style.
27
 
28
   Commenting is Doxygen compatible.                                         */
29
/*---------------------------------------------------------------------------*/
30
 
31 225 jeremybenn
/* GDB signal numbers */
32
#define TARGET_SIGNAL_NONE  0           /*!< No signal */
33
#define TARGET_SIGNAL_TRAP  5           /*!< Breakpoint hit */
34 147 jeremybenn
 
35
/*! Number of registers */
36
#define  OR32_MAX_GPRS  32
37
 
38
/* Particular registers */
39
#define OR32_FIRST_ARG_REGNUM  3                        /*!< First arg reg */
40
#define OR32_PPC_REGNUM        (OR32_MAX_GPRS + 0)      /*!< Previous PC */
41
#define OR32_NPC_REGNUM        (OR32_MAX_GPRS + 1)      /*!< Next PC */
42
#define OR32_SR_REGNUM         (OR32_MAX_GPRS + 2)      /*!< Supervision Reg */
43
 
44 225 jeremybenn
/* Debug SPRs */
45
#define OR32_SPR_NPC    0x0010          /*!< Next Program Counter */
46
#define OR32_SPR_SR     0x0011          /*!< Supervision Register */
47
#define OR32_SPR_PPC    0x0012          /*!< Previous Program Counter */
48 147 jeremybenn
 
49 225 jeremybenn
#define OR32_SPR_DMR1   0x3010          /*!< Debug Mode Register 1 */
50
#define OR32_SPR_DMR2   0x3011          /*!< Debug Mode Register 2 */
51
#define OR32_SPR_DSR    0x3014          /*!< Debug Stop Register */
52
#define OR32_SPR_DRR    0x3015          /*!< Debug Reason Register */
53
 
54
/* Debug SPR bit fields */
55
#define OR32_SPR_DMR1_ST   0x00400000   /*!< Single-step trace*/
56
#define OR32_SPR_DMR2_WGB  0x003ff000   /*!< Watchpoints which breakpoint */
57
#define OR32_SPR_DSR_TE    0x00002000   /*!< Trap exception bit */
58
 
59
/* OR1K exception vector addresses */
60
#define OR32_RESET_EXCEPTION  0x100     /*!< Reset exception vector */
61
 
62 147 jeremybenn
/* ------------------------------------------------------------------------- */
63
/*!A structure to hold the state of a simulation instance.
64
 
65
   This is the typedef SIM_DESC.
66
 
67
   The entries are
68 225 jeremybenn
   - A flag which is true if we are used for debug rather than standalone (i.e
69
     we were opened with type SIM_OPEN_DEBUG)
70
   - The callback function supplied to the sim_open () function
71
   - This simulator's name (argv[0] supplied to sim_open ()
72
   - A flag to indicate the simulator has been opened.
73
   - The last reason the simulator stopped
74
   - The signal associated with the last stop, or the exit code from the last
75
     exit.
76
   - The entry point to the program if available, otherwise the reset
77
     exception vector address.
78
   - The NPC with which to resume. So as not to destroy the pipeline, this is
79
     only written immediately before unstalling.                             */
80 147 jeremybenn
/* ------------------------------------------------------------------------- */
81
struct sim_state
82
{
83
  int                          is_debug;
84
  struct host_callback_struct *callback;
85
  char                        *myname;
86 225 jeremybenn
  int                          sim_open;
87
  enum sim_stop                last_reason;
88
  unsigned int                 last_rc;
89
  unsigned long int            entry_point;
90
  unsigned long int            resume_npc;
91
 
92 147 jeremybenn
};
93
 
94
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.