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jeremybenn |
/* e500 registers, for PSIM, the PowerPC simulator.
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Copyright 2003, 2007, 2008 Free Software Foundation, Inc.
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Contributed by Red Hat Inc; developed under contract from Motorola.
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Written by matthew green <mrg@redhat.com>.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* e500 accumulator. */
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typedef unsigned64 accreg;
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enum {
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msr_e500_spu_enable = BIT(38)
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};
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/* E500 regsiters. */
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enum
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{
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spefscr_sovh = BIT(32), /* summary integer overlow (high) */
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spefscr_ovh = BIT(33), /* int overflow (high) */
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spefscr_fgh = BIT(34), /* FP guard (high) */
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spefscr_fxh = BIT(35), /* FP sticky (high) */
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spefscr_finvh = BIT(36), /* FP invalid operand (high) */
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spefscr_fdbzh = BIT(37), /* FP divide by zero (high) */
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spefscr_funfh = BIT(38), /* FP underflow (high) */
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spefscr_fovfh = BIT(39), /* FP overflow (high) */
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spefscr_finxs = BIT(42), /* FP inexact sticky */
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spefscr_finvs = BIT(43), /* FP invalid operand sticky */
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spefscr_fdbzs = BIT(44), /* FP divide by zero sticky */
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spefscr_funfs = BIT(45), /* FP underflow sticky */
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spefscr_fovfs = BIT(46), /* FP overflow sticky */
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spefscr_mode = BIT(47), /* SPU MODE (read only) */
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spefscr_sov = BIT(48), /* Summary integer overlow (low) */
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spefscr_ov = BIT(49), /* int overflow (low) */
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spefscr_fg = BIT(50), /* FP guard (low) */
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spefscr_fx = BIT(51), /* FP sticky (low) */
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spefscr_finv = BIT(52), /* FP invalid operand (low) */
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spefscr_fdbz = BIT(53), /* FP divide by zero (low) */
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spefscr_funf = BIT(54), /* FP underflow (low) */
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spefscr_fovf = BIT(55), /* FP overflow (low) */
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spefscr_finxe = BIT(57), /* FP inexact enable */
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spefscr_finve = BIT(58), /* FP invalid operand enable */
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spefscr_fdbze = BIT(59), /* FP divide by zero enable */
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spefscr_funfe = BIT(60), /* FP underflow enable */
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spefscr_fovfe = BIT(61), /* FP overflow enable */
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spefscr_frmc0 = BIT(62), /* FP round mode control */
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spefscr_frmc1 = BIT(63),
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spefscr_frmc = (spefscr_frmc0 | spefscr_frmc1),
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};
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struct e500_regs {
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/* e500 high bits. */
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signed_word gprh[32];
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/* Accumulator */
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accreg acc;
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};
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/* SPE partially visible acculator */
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#define ACC cpu_registers(processor)->e500.acc
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/* e500 register high bits */
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#define GPRH(N) cpu_registers(processor)->e500.gprh[N]
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/* e500 unified vector register
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We need to cast the gpr value to an unsigned type so that it
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doesn't get sign-extended when it's or-ed with a 64-bit value; that
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would wipe out the upper 32 bits of the register's value. */
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#define EVR(N) ((((unsigned64)GPRH(N)) << 32) | (unsigned32) GPR(N))
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