OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [ppc/] [vm.h] - Blame information for rev 252

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
/*  This file is part of the program psim.
2
 
3
    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
4
 
5
    This program is free software; you can redistribute it and/or modify
6
    it under the terms of the GNU General Public License as published by
7
    the Free Software Foundation; either version 2 of the License, or
8
    (at your option) any later version.
9
 
10
    This program is distributed in the hope that it will be useful,
11
    but WITHOUT ANY WARRANTY; without even the implied warranty of
12
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
    GNU General Public License for more details.
14
 
15
    You should have received a copy of the GNU General Public License
16
    along with this program; if not, write to the Free Software
17
    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18
 
19
    */
20
 
21
 
22
#ifndef _VM_H_
23
#define _VM_H_
24
 
25
typedef struct _vm vm;
26
typedef struct _vm_data_map vm_data_map;
27
typedef struct _vm_instruction_map vm_instruction_map;
28
 
29
 
30
/* each PowerPC requires two virtual memory maps */
31
 
32
INLINE_VM\
33
(vm *) vm_create
34
(core *memory);
35
 
36
INLINE_VM\
37
(vm_data_map *) vm_create_data_map
38
(vm *memory);
39
 
40
INLINE_VM\
41
(vm_instruction_map *) vm_create_instruction_map
42
(vm *memory);
43
 
44
 
45
/* address translation, if the translation is invalid
46
   these will not return */
47
 
48
INLINE_VM\
49
(unsigned_word) vm_real_data_addr
50
(vm_data_map *data_map,
51
 unsigned_word ea,
52
 int is_read,
53
 cpu *processor,
54
 unsigned_word cia);
55
 
56
INLINE_VM\
57
(unsigned_word) vm_real_instruction_addr
58
(vm_instruction_map *instruction_map,
59
 cpu *processor,
60
 unsigned_word cia);
61
 
62
 
63
/* generic block transfers.  Dependant on the presence of the
64
   PROCESSOR arg, either returns the number of bytes transfered or (if
65
   PROCESSOR is non NULL) aborts the simulation */
66
 
67
INLINE_VM\
68
(int) vm_data_map_read_buffer
69
(vm_data_map *map,
70
 void *target,
71
 unsigned_word addr,
72
 unsigned len,
73
 cpu *processor,
74
 unsigned_word cia);
75
 
76
INLINE_VM\
77
(int) vm_data_map_write_buffer
78
(vm_data_map *map,
79
 const void *source,
80
 unsigned_word addr,
81
 unsigned len,
82
 int violate_read_only_section,
83
 cpu *processor,
84
 unsigned_word cia);
85
 
86
 
87
/* fetch the next instruction from memory */
88
 
89
INLINE_VM\
90
(instruction_word) vm_instruction_map_read
91
(vm_instruction_map *instruction_map,
92
 cpu *processor,
93
 unsigned_word cia);
94
 
95
 
96
/* read data from memory */
97
 
98
#define DECLARE_VM_DATA_MAP_READ_N(N) \
99
INLINE_VM\
100
(unsigned_##N) vm_data_map_read_##N \
101
(vm_data_map *map, \
102
 unsigned_word ea, \
103
 cpu *processor, \
104
 unsigned_word cia);
105
 
106
DECLARE_VM_DATA_MAP_READ_N(1)
107
DECLARE_VM_DATA_MAP_READ_N(2)
108
DECLARE_VM_DATA_MAP_READ_N(4)
109
DECLARE_VM_DATA_MAP_READ_N(8)
110
DECLARE_VM_DATA_MAP_READ_N(word)
111
 
112
 
113
/* write data to memory */
114
 
115
#define DECLARE_VM_DATA_MAP_WRITE_N(N) \
116
INLINE_VM\
117
(void) vm_data_map_write_##N \
118
(vm_data_map *map, \
119
 unsigned_word addr, \
120
 unsigned_##N val, \
121
 cpu *processor, \
122
 unsigned_word cia);
123
 
124
DECLARE_VM_DATA_MAP_WRITE_N(1)
125
DECLARE_VM_DATA_MAP_WRITE_N(2)
126
DECLARE_VM_DATA_MAP_WRITE_N(4)
127
DECLARE_VM_DATA_MAP_WRITE_N(8)
128
DECLARE_VM_DATA_MAP_WRITE_N(word)
129
 
130
 
131
/* update vm data structures due to a synchronization point */
132
 
133
INLINE_VM\
134
(void) vm_synchronize_context
135
(vm *memory,
136
 spreg *sprs,
137
 sreg *srs,
138
 msreg msr,
139
 /**/
140
 cpu *processor,
141
 unsigned_word cia);
142
 
143
 
144
/* update vm data structures due to a TLB operation */
145
 
146
INLINE_VM\
147
(void) vm_page_tlb_invalidate_entry
148
(vm *memory,
149
 unsigned_word ea);
150
 
151
INLINE_VM\
152
(void) vm_page_tlb_invalidate_all
153
(vm *memory);
154
 
155
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.