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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [sh64/] [cpu.h] - Blame information for rev 281

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1 24 jeremybenn 
/* CPU family header for sh64.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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5 
Copyright 1996-2005 Free Software Foundation, Inc.
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7 
This file is part of the GNU simulators.
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9 
This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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14 
This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.
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22 
*/
23 
 
24 
#ifndef CPU_SH64_H
25 
#define CPU_SH64_H
26 
 
27 
/* Maximum number of instructions that are fetched at a time.
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   This is for LIW type instructions sets (e.g. m32r).  */
29 
#define MAX_LIW_INSNS 1
30 
 
31 
/* Maximum number of instructions that can be executed in parallel.  */
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#define MAX_PARALLEL_INSNS 1
33 
 
34 
/* CPU state information.  */
35 
typedef struct {
36 
  /* Hardware elements.  */
37 
  struct {
38 
  /* Program counter */
39 
  UDI h_pc;
40 
#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) \
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do { \
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{\
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CPU (h_ism) = ANDDI ((x), 1);\
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CPU (h_pc) = ANDDI ((x), INVDI (1));\
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}\
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;} while (0)
48 
  /* General purpose integer registers */
49 
  DI h_gr[64];
50 
#define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index])))
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#define SET_H_GR(index, x) \
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do { \
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if ((((index)) != (63))) {\
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CPU (h_gr[(index)]) = (x);\
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} else {\
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((void) 0); /*nop*/\
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}\
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;} while (0)
59 
  /* Control registers */
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  DI h_cr[64];
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#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index])))
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#define SET_H_CR(index, x) \
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do { \
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if ((((index)) == (0))) {\
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CPU (h_sr) = (x);\
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} else {\
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CPU (h_cr[(index)]) = (x);\
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}\
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;} while (0)
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  /* Status register */
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  SI h_sr;
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#define GET_H_SR() CPU (h_sr)
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#define SET_H_SR(x) (CPU (h_sr) = (x))
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  /* Floating point status and control register */
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  SI h_fpscr;
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#define GET_H_FPSCR() CPU (h_fpscr)
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#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x))
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  /* Single precision floating point registers */
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  SF h_fr[64];
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#define GET_H_FR(a1) CPU (h_fr)[a1]
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#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
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  /* Single/Double precision floating point registers */
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  DF h_fsd[16];
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#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), CPU (h_fr[index]))))
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#define SET_H_FSD(index, x) \
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do { \
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if (GET_H_PRBIT ()) {\
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SET_H_DRC ((index), (x));\
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} else {\
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SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\
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}\
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;} while (0)
93 
  /* floating point registers for fmov */
94 
  DF h_fmov[16];
95 
#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index)))))
96 
#define SET_H_FMOV(index, x) \
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do { \
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if (NOTBI (GET_H_SZBIT ())) {\
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SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), (x)));\
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} else {\
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if ((((((index)) & (1))) == (1))) {\
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SET_H_XD ((((index)) & ((~ (1)))), (x));\
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} else {\
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SET_H_DR ((index), (x));\
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}\
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}\
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;} while (0)
108 
  /* Branch target registers */
109 
  DI h_tr[8];
110 
#define GET_H_TR(a1) CPU (h_tr)[a1]
111 
#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x))
112 
  /* Current instruction set mode */
113 
  BI h_ism;
114 
#define GET_H_ISM() CPU (h_ism)
115 
#define SET_H_ISM(x) \
116 
do { \
117 
cgen_rtx_error (current_cpu, "cannot set ism directly");\
118 
;} while (0)
119 
  } hardware;
120 
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
121 
} SH64_CPU_DATA;
122 
 
123 
/* Virtual regs.  */
124 
 
125 
#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
126 
#define SET_H_GRC(index, x) \
127 
do { \
128 
CPU (h_gr[(index)]) = EXTSIDI ((x));\
129 
;} while (0)
130 
#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1)
131 
#define SET_H_FRBIT(x) \
132 
do { \
133 
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\
134 
;} while (0)
135 
#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1)
136 
#define SET_H_SZBIT(x) \
137 
do { \
138 
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\
139 
;} while (0)
140 
#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1)
141 
#define SET_H_PRBIT(x) \
142 
do { \
143 
CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\
144 
;} while (0)
145 
#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
146 
#define SET_H_SBIT(x) \
147 
do { \
148 
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\
149 
;} while (0)
150 
#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1)
151 
#define SET_H_MBIT(x) \
152 
do { \
153 
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
154 
;} while (0)
155 
#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1)
156 
#define SET_H_QBIT(x) \
157 
do { \
158 
CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
159 
;} while (0)
160 
#define GET_H_FP(index) CPU (h_fr[index])
161 
#define SET_H_FP(index, x) \
162 
do { \
163 
CPU (h_fr[(index)]) = (x);\
164 
;} while (0)
165 
#define GET_H_FV(index) CPU (h_fr[index])
166 
#define SET_H_FV(index, x) \
167 
do { \
168 
CPU (h_fr[(index)]) = (x);\
169 
;} while (0)
170 
#define GET_H_FMTX(index) CPU (h_fr[index])
171 
#define SET_H_FMTX(index, x) \
172 
do { \
173 
CPU (h_fr[(index)]) = (x);\
174 
;} while (0)
175 
#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
176 
#define SET_H_DR(index, x) \
177 
do { \
178 
{\
179 
CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\
180 
CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\
181 
}\
182 
;} while (0)
183 
#define GET_H_ENDIAN() sh64_endian (current_cpu)
184 
#define SET_H_ENDIAN(x) \
185 
do { \
186 
cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\
187 
;} while (0)
188 
#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
189 
#define SET_H_FRC(index, x) \
190 
do { \
191 
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
192 
;} while (0)
193 
#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index)))
194 
#define SET_H_DRC(index, x) \
195 
do { \
196 
SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\
197 
;} while (0)
198 
#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))])
199 
#define SET_H_XF(index, x) \
200 
do { \
201 
CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\
202 
;} while (0)
203 
#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index)))
204 
#define SET_H_XD(index, x) \
205 
do { \
206 
SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
207 
;} while (0)
208 
#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
209 
#define SET_H_FVC(index, x) \
210 
do { \
211 
CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
212 
;} while (0)
213 
#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
214 
#define SET_H_GBR(x) \
215 
do { \
216 
CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
217 
;} while (0)
218 
#define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1)
219 
#define SET_H_VBR(x) \
220 
do { \
221 
CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\
222 
;} while (0)
223 
#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
224 
#define SET_H_PR(x) \
225 
do { \
226 
CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\
227 
;} while (0)
228 
#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)
229 
#define SET_H_MACL(x) \
230 
do { \
231 
CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\
232 
;} while (0)
233 
#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)
234 
#define SET_H_MACH(x) \
235 
do { \
236 
CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\
237 
;} while (0)
238 
#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1)
239 
#define SET_H_TBIT(x) \
240 
do { \
241 
CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\
242 
;} while (0)
243 
 
244 
/* Cover fns for register access.  */
245 
UDI sh64_h_pc_get (SIM_CPU *);
246 
void sh64_h_pc_set (SIM_CPU *, UDI);
247 
DI sh64_h_gr_get (SIM_CPU *, UINT);
248 
void sh64_h_gr_set (SIM_CPU *, UINT, DI);
249 
SI sh64_h_grc_get (SIM_CPU *, UINT);
250 
void sh64_h_grc_set (SIM_CPU *, UINT, SI);
251 
DI sh64_h_cr_get (SIM_CPU *, UINT);
252 
void sh64_h_cr_set (SIM_CPU *, UINT, DI);
253 
SI sh64_h_sr_get (SIM_CPU *);
254 
void sh64_h_sr_set (SIM_CPU *, SI);
255 
SI sh64_h_fpscr_get (SIM_CPU *);
256 
void sh64_h_fpscr_set (SIM_CPU *, SI);
257 
BI sh64_h_frbit_get (SIM_CPU *);
258 
void sh64_h_frbit_set (SIM_CPU *, BI);
259 
BI sh64_h_szbit_get (SIM_CPU *);
260 
void sh64_h_szbit_set (SIM_CPU *, BI);
261 
BI sh64_h_prbit_get (SIM_CPU *);
262 
void sh64_h_prbit_set (SIM_CPU *, BI);
263 
BI sh64_h_sbit_get (SIM_CPU *);
264 
void sh64_h_sbit_set (SIM_CPU *, BI);
265 
BI sh64_h_mbit_get (SIM_CPU *);
266 
void sh64_h_mbit_set (SIM_CPU *, BI);
267 
BI sh64_h_qbit_get (SIM_CPU *);
268 
void sh64_h_qbit_set (SIM_CPU *, BI);
269 
SF sh64_h_fr_get (SIM_CPU *, UINT);
270 
void sh64_h_fr_set (SIM_CPU *, UINT, SF);
271 
SF sh64_h_fp_get (SIM_CPU *, UINT);
272 
void sh64_h_fp_set (SIM_CPU *, UINT, SF);
273 
SF sh64_h_fv_get (SIM_CPU *, UINT);
274 
void sh64_h_fv_set (SIM_CPU *, UINT, SF);
275 
SF sh64_h_fmtx_get (SIM_CPU *, UINT);
276 
void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
277 
DF sh64_h_dr_get (SIM_CPU *, UINT);
278 
void sh64_h_dr_set (SIM_CPU *, UINT, DF);
279 
DF sh64_h_fsd_get (SIM_CPU *, UINT);
280 
void sh64_h_fsd_set (SIM_CPU *, UINT, DF);
281 
DF sh64_h_fmov_get (SIM_CPU *, UINT);
282 
void sh64_h_fmov_set (SIM_CPU *, UINT, DF);
283 
DI sh64_h_tr_get (SIM_CPU *, UINT);
284 
void sh64_h_tr_set (SIM_CPU *, UINT, DI);
285 
BI sh64_h_endian_get (SIM_CPU *);
286 
void sh64_h_endian_set (SIM_CPU *, BI);
287 
BI sh64_h_ism_get (SIM_CPU *);
288 
void sh64_h_ism_set (SIM_CPU *, BI);
289 
SF sh64_h_frc_get (SIM_CPU *, UINT);
290 
void sh64_h_frc_set (SIM_CPU *, UINT, SF);
291 
DF sh64_h_drc_get (SIM_CPU *, UINT);
292 
void sh64_h_drc_set (SIM_CPU *, UINT, DF);
293 
SF sh64_h_xf_get (SIM_CPU *, UINT);
294 
void sh64_h_xf_set (SIM_CPU *, UINT, SF);
295 
DF sh64_h_xd_get (SIM_CPU *, UINT);
296 
void sh64_h_xd_set (SIM_CPU *, UINT, DF);
297 
SF sh64_h_fvc_get (SIM_CPU *, UINT);
298 
void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
299 
SI sh64_h_gbr_get (SIM_CPU *);
300 
void sh64_h_gbr_set (SIM_CPU *, SI);
301 
SI sh64_h_vbr_get (SIM_CPU *);
302 
void sh64_h_vbr_set (SIM_CPU *, SI);
303 
SI sh64_h_pr_get (SIM_CPU *);
304 
void sh64_h_pr_set (SIM_CPU *, SI);
305 
SI sh64_h_macl_get (SIM_CPU *);
306 
void sh64_h_macl_set (SIM_CPU *, SI);
307 
SI sh64_h_mach_get (SIM_CPU *);
308 
void sh64_h_mach_set (SIM_CPU *, SI);
309 
BI sh64_h_tbit_get (SIM_CPU *);
310 
void sh64_h_tbit_set (SIM_CPU *, BI);
311 
 
312 
/* These must be hand-written.  */
313 
extern CPUREG_FETCH_FN sh64_fetch_register;
314 
extern CPUREG_STORE_FN sh64_store_register;
315 
 
316 
typedef struct {
317 
  int empty;
318 
} MODEL_SH4_DATA;
319 
 
320 
typedef struct {
321 
  int empty;
322 
} MODEL_SH5_DATA;
323 
 
324 
typedef struct {
325 
  int empty;
326 
} MODEL_SH5_MEDIA_DATA;
327 
 
328 
/* Collection of various things for the trace handler to use.  */
329 
 
330 
typedef struct trace_record {
331 
  IADDR pc;
332 
  /* FIXME:wip */
333 
} TRACE_RECORD;
334 
 
335 
#endif /* CPU_SH64_H */

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