URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Details |
Compare with Previous |
View Log
Line No. |
Rev |
Author |
Line |
1 |
24 |
jeremybenn |
/* engine configuration for sh64 */
|
2 |
|
|
|
3 |
|
|
/* WITH_FAST: non-zero if a fast version of the engine is available
|
4 |
|
|
in addition to the full-featured version. */
|
5 |
|
|
#define WITH_FAST 1
|
6 |
|
|
|
7 |
|
|
/* WITH_SCACHE_PBB_SH64_COMPACT: non-zero if the pbb engine was selected. */
|
8 |
|
|
#define WITH_SCACHE_PBB_SH64_COMPACT 1
|
9 |
|
|
|
10 |
|
|
/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn. */
|
11 |
|
|
#define HAVE_PARALLEL_INSNS 0
|
12 |
|
|
#define WITH_PARALLEL_READ 0
|
13 |
|
|
#define WITH_PARALLEL_WRITE 0
|
14 |
|
|
#define WITH_PARALLEL_GENWRITE 0
|
15 |
|
|
|
16 |
|
|
/* WITH_SEM_SWITCH_FULL: non-zero if full-featured engine is
|
17 |
|
|
implemented as a switch(). */
|
18 |
|
|
#define WITH_SEM_SWITCH_FULL 0
|
19 |
|
|
|
20 |
|
|
/* WITH_SEM_SWITCH_FAST: non-zero if fast engine is
|
21 |
|
|
implemented as a switch(). */
|
22 |
|
|
#define WITH_SEM_SWITCH_FAST 1
|
23 |
|
|
|
24 |
|
|
/* Functions defined in the generated mainloop.c file
|
25 |
|
|
(which doesn't necessarily have that file name). */
|
26 |
|
|
|
27 |
|
|
extern ENGINE_FN sh64_compact_engine_run_full;
|
28 |
|
|
extern ENGINE_FN sh64_compact_engine_run_fast;
|
29 |
|
|
|
30 |
|
|
extern SEM_PC sh64_compact_pbb_begin (SIM_CPU *, int);
|
31 |
|
|
extern SEM_PC sh64_compact_pbb_chain (SIM_CPU *, SEM_ARG);
|
32 |
|
|
extern SEM_PC sh64_compact_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);
|
33 |
|
|
extern void sh64_compact_pbb_before (SIM_CPU *, SCACHE *);
|
34 |
|
|
extern void sh64_compact_pbb_after (SIM_CPU *, SCACHE *);
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.