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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [sh64/] [sim-if.c] - Blame information for rev 301

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Line No. Rev Author Line
1 24 jeremybenn
/* Main simulator entry points specific to the SH5.
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   Copyright (C) 2000, 2008 Free Software Foundation, Inc.
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   Contributed by Cygnus Solutions.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
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#include "libiberty.h"
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#include "bfd.h"
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#include "sim-main.h"
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#ifdef HAVE_STDLIB_H
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#include <stdlib.h>
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#endif
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#include "sim-options.h"
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#include "dis-asm.h"
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static void free_state (SIM_DESC);
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/* Since we don't build the cgen-opcode table, we use a wrapper around
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   the existing disassembler from libopcodes. */
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static CGEN_DISASSEMBLER sh64_disassemble_insn;
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/* Records simulator descriptor so utilities like sh5_dump_regs can be
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   called from gdb.  */
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SIM_DESC current_state;
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/* Cover function of sim_state_free to free the cpu buffers as well.  */
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static void
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free_state (SIM_DESC sd)
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{
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  if (STATE_MODULES (sd) != NULL)
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    sim_module_uninstall (sd);
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  sim_cpu_free_all (sd);
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  sim_state_free (sd);
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}
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/* Create an instance of the simulator.  */
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SIM_DESC
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sim_open (kind, callback, abfd, argv)
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     SIM_OPEN_KIND kind;
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     host_callback *callback;
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     struct bfd *abfd;
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     char **argv;
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{
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  char c;
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  int i;
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  SIM_DESC sd = sim_state_alloc (kind, callback);
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  /* The cpu data is kept in a separately allocated chunk of memory.  */
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  if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
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    {
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      free_state (sd);
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      return 0;
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    }
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#if 0 /* FIXME: pc is in mach-specific struct */
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  /* FIXME: watchpoints code shouldn't need this */
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  {
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    SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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    STATE_WATCHPOINTS (sd)->pc = &(PC);
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    STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
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  }
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#endif
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  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
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    {
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      free_state (sd);
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      return 0;
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    }
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#if 0 /* FIXME: 'twould be nice if we could do this */
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  /* These options override any module options.
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     Obviously ambiguity should be avoided, however the caller may wish to
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     augment the meaning of an option.  */
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  if (extra_options != NULL)
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    sim_add_option_table (sd, extra_options);
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#endif
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  /* getopt will print the error message so we just have to exit if this fails.
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     FIXME: Hmmm...  in the case of gdb we need getopt to call
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     print_filtered.  */
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  if (sim_parse_args (sd, argv) != SIM_RC_OK)
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    {
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      free_state (sd);
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      return 0;
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    }
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  /* Allocate core managed memory if none specified by user.
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     Use address 4 here in case the user wanted address 0 unmapped.  */
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  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
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    sim_do_commandf (sd, "memory region 0,0x%x", SH64_DEFAULT_MEM_SIZE);
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  /* Add a small memory region way up in the address space to handle
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     writes to invalidate an instruction cache line.  This is used for
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     trampolines.  Since we don't simulate the cache, this memory just
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     avoids bus errors.  64K ought to do. */
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  sim_do_command (sd," memory region 0xf0000000,0x10000");
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  /* check for/establish the reference program image */
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  if (sim_analyze_program (sd,
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                           (STATE_PROG_ARGV (sd) != NULL
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                            ? *STATE_PROG_ARGV (sd)
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                            : NULL),
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                           abfd) != SIM_RC_OK)
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    {
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      free_state (sd);
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      return 0;
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    }
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  /* Establish any remaining configuration options.  */
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  if (sim_config (sd) != SIM_RC_OK)
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    {
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      free_state (sd);
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      return 0;
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    }
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  if (sim_post_argv_init (sd) != SIM_RC_OK)
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    {
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      free_state (sd);
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      return 0;
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    }
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  /* Open a copy of the cpu descriptor table.  */
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  {
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    CGEN_CPU_DESC cd = sh_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
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                                              CGEN_ENDIAN_BIG);
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    for (i = 0; i < MAX_NR_PROCESSORS; ++i)
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      {
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        SIM_CPU *cpu = STATE_CPU (sd, i);
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        CPU_CPU_DESC (cpu) = cd;
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        CPU_DISASSEMBLER (cpu) = sh64_disassemble_insn;
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      }
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  }
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  /* Clear idesc table pointers for good measure. */
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  sh64_idesc_media = sh64_idesc_compact = NULL;
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  /* Initialize various cgen things not done by common framework.
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     Must be done after sh_cgen_cpu_open.  */
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  cgen_init (sd);
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  /* Store in a global so things like sparc32_dump_regs can be invoked
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     from the gdb command line.  */
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  current_state = sd;
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  return sd;
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}
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void
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sim_close (sd, quitting)
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     SIM_DESC sd;
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     int quitting;
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{
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  sh_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
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  sim_module_uninstall (sd);
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}
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SIM_RC
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sim_create_inferior (sd, abfd, argv, envp)
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     SIM_DESC sd;
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     struct bfd *abfd;
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     char **argv;
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     char **envp;
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{
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  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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  SIM_ADDR addr;
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  if (abfd != NULL)
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    addr = bfd_get_start_address (abfd);
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  else
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    addr = 0;
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  sim_pc_set (current_cpu, addr);
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#if 0
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  STATE_ARGV (sd) = sim_copy_argv (argv);
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  STATE_ENVP (sd) = sim_copy_argv (envp);
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#endif
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  return SIM_RC_OK;
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}
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void
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sim_do_command (sd, cmd)
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     SIM_DESC sd;
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     char *cmd;
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{
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  if (sim_args_command (sd, cmd) != SIM_RC_OK)
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    sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
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}
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/* Disassemble an instruction.  */
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static void
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sh64_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
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                       const ARGBUF *abuf, IADDR pc, char *buf)
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{
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  struct disassemble_info disasm_info;
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  SFILE sfile;
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  SIM_DESC sd = CPU_STATE (cpu);
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  sfile.buffer = sfile.current = buf;
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  INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
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                         (fprintf_ftype) sim_disasm_sprintf);
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  disasm_info.arch = bfd_get_arch (STATE_PROG_BFD (sd));
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  disasm_info.mach = bfd_get_mach (STATE_PROG_BFD (sd));
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  disasm_info.endian =
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    (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
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     : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
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     : BFD_ENDIAN_UNKNOWN);
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  disasm_info.read_memory_func = sim_disasm_read_memory;
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  disasm_info.memory_error_func = sim_disasm_perror_memory;
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  disasm_info.application_data = (PTR) cpu;
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  if (sh64_h_ism_get (cpu) == ISM_MEDIA)
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    print_insn_sh64x_media (pc, &disasm_info);
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  else
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    print_insn_sh (pc, &disasm_info);
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}

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