OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [common/] [Makefile.in] - Blame information for rev 437

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 131 jeremybenn
CC=gcc
2
CFLAGS = -Wall -Werror -I../../common -I../../../include -g
3
default: check
4
 
5
 
6
# Verify SIM-BITS
7
 
8
check: bits32m0.ok bits32m31.ok bits64m0.ok bits64m63.ok
9
all: bits32m0 bits32m31 bits64m0 bits64m63
10
 
11
bits32m0.c: bits-gen bits-tst.c
12
        ./bits-gen 32 0 big > tmp-bits32m0.c
13
        cat bits-tst.c >> tmp-bits32m0.c
14
        mv tmp-bits32m0.c bits32m0.c
15
bits32m31.c: bits-gen bits-tst.c
16
        ./bits-gen 32 31 little > tmp-bits32m31.c
17
        cat bits-tst.c >> tmp-bits32m31.c
18
        mv tmp-bits32m31.c bits32m31.c
19
bits64m0.c: bits-gen bits-tst.c
20
        ./bits-gen 64 0 big > tmp-bits64m0.c
21
        cat bits-tst.c >> tmp-bits64m0.c
22
        mv tmp-bits64m0.c bits64m0.c
23
bits64m63.c: bits-gen bits-tst.c
24
        ./bits-gen 64 63 little > tmp-bits64m63.c
25
        cat bits-tst.c >> tmp-bits64m63.c
26
        mv tmp-bits64m63.c bits64m63.c
27
 
28
 
29
 
30
# Verify SIM-FPU
31
#
32
#check: fpu-tst.ok
33
#all: fpu-tst
34
 
35
 
36
 
37
# Verify SIM-ALU
38
 
39
check: alu-tst.ok
40
all: alu-tst
41
alu-tst.o: alu-tst.c alu-n-tst.h
42
 
43
clean:
44
        rm -f *.o
45
        rm -f *.ok
46
        rm -f bits32m0 bits32m31 bits64m0 bits64m63 bits-gen
47
        rm -f tmp-*
48
        rm -f alu-tst
49
 
50
.SUFIXES: .ok
51
%.ok: %
52
        ./$<
53
        touch $<.ok

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.