OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [d10v-elf/] [t-sadd.s] - Blame information for rev 298

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
.include "t-macros.i"
2
 
3
        start
4
 
5
        PSW_BITS = PSW_FX|PSW_ST|PSW_SM
6
        loadpsw2 PSW_BITS
7
 
8
 ;; Test normal sadd
9
 
10
        loadacc2 a0 0x00 0x7fff 0xffff
11
        loadacc2 a1 0xff 0x8000 0x0000
12
        sadd a1, a0
13
        checkacc2 1 a0 0x00 0x7fff 0xffff
14
        checkacc2 2 a1 0xff 0x8000 0x7fff
15
 
16
 ;; Test overflow 
17
 
18
        loadacc2 a0 0x00 0x0000 0x0000
19
        loadacc2 a1 0x01 0x8000 0x0000
20
        sadd a1, a0
21
        checkacc2 3 a0 0x00 0x0000 0x0000
22
        checkacc2 4 a1 0x00 0x7fff 0xffff
23
 
24
        loadacc2 a0 0x00 0xffff 0xffff
25
        loadacc2 a1 0x00 0xffff 0xffff
26
        sadd a1, a0
27
        checkacc2 5 a1 0x00 0x7fff 0xffff
28
        checkacc2 6 a0 0x00 0xffff 0xffff
29
 
30
 ;; Test underflow
31
 
32
        loadacc2 a0 0x00 0x0000 0x0000
33
        loadacc2 a1 0x80 0x8000 0x0000
34
        sadd a1, a0
35
        checkacc2 7 a0 0x00 0x0000 0x0000
36
        checkacc2 8 a1 0xff 0x8000 0x0000
37
 
38
        exit0

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.