OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [frv-elf/] [cache.s] - Blame information for rev 450

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# run with --memory-region 0xff000000,4 --memory-region 0xfe000000,00404000
2
; Exit with return code
3
        .macro exit rc
4
        setlos.p        #1,gr7
5
        setlos          \rc,gr8
6
        tira            gr0,#0
7
        .endm
8
 
9
; Pass the test case
10
        .macro pass
11
pass:
12
        setlos.p        #5,gr10
13
        setlos          #1,gr8
14
        setlos          #5,gr7
15
        sethi.p         %hi(passmsg),gr9
16
        setlo           %lo(passmsg),gr9
17
        tira            gr0,#0
18
        exit            #0
19
        .endm
20
 
21
; Fail the testcase
22
        .macro fail
23
fail\@:
24
        setlos.p        #5,gr10
25
        setlos          #1,gr8
26
        setlos          #5,gr7
27
        sethi.p         %hi(failmsg),gr9
28
        setlo           %lo(failmsg),gr9
29
        tira            gr0,#0
30
        exit            #1
31
        .endm
32
 
33
        .data
34
failmsg:
35
        .ascii "fail\n"
36
passmsg:
37
        .ascii "pass\n"
38
 
39
        .text
40
        .global _start
41
_start:
42
        movsg           hsr0,gr10       ; enable insn and data caches
43
        sethi.p         0xc800,gr11     ; in copy-back mode
44
        setlo           0x0000,gr11
45
        or              gr10,gr11,gr10
46
        movgs           gr10,hsr0
47
 
48
        sethi.p         0x7,sp
49
        setlo           0x0000,sp
50
 
51
        ; fill the cache
52
        sethi.p         %hi(done1),gr10
53
        setlo           %lo(done1),gr10
54
        movgs           gr10,lr
55
        setlos.p        0x1000,gr10
56
        setlos          0x0,gr11
57
        movgs           gr10,lcr
58
write1: st.p            gr11,@(sp,gr11)
59
        addi.p          gr11,4,gr11
60
        bctrlr.p        1,0
61
        bra             write1
62
done1:
63
        ; read it back
64
        sethi.p         %hi(done2),gr10
65
        setlo           %lo(done2),gr10
66
        movgs           gr10,lr
67
        setlos.p        0x1000,gr10
68
        setlos          0x0,gr11
69
        movgs           gr10,lcr
70
read1:  ld              @(sp,gr11),gr12
71
        cmp             gr11,gr12,icc0
72
        bne             icc0,1,fail
73
        addi.p          gr11,4,gr11
74
        bctrlr.p        1,0
75
        bra             read1
76
done2:
77
 
78
        ; fill the cache twice
79
        sethi.p         %hi(done3),gr10
80
        setlo           %lo(done3),gr10
81
        movgs           gr10,lr
82
        setlos.p        0x2000,gr10
83
        setlos          0x0,gr11
84
        movgs           gr10,lcr
85
write3: st.p            gr11,@(sp,gr11)
86
        addi.p          gr11,4,gr11
87
        bctrlr.p        1,0
88
        bra             write3
89
done3:
90
        ; read it back
91
        sethi.p         %hi(done4),gr10
92
        setlo           %lo(done4),gr10
93
        movgs           gr10,lr
94
        setlos.p        0x2000,gr10
95
        setlos          0x0,gr11
96
        movgs           gr10,lcr
97
read4:  ld              @(sp,gr11),gr12
98
        cmp             gr11,gr12,icc0
99
        bne             icc0,1,fail
100
        addi.p          gr11,4,gr11
101
        bctrlr.p        1,0
102
        bra             read4
103
done4:
104
        ; read it back in reverse
105
        sethi.p         %hi(done5),gr10
106
        setlo           %lo(done5),gr10
107
        movgs           gr10,lr
108
        setlos.p        0x2000,gr10
109
        setlos          0x7ffc,gr11
110
        movgs           gr10,lcr
111
read5:  ld              @(sp,gr11),gr12
112
        cmp             gr11,gr12,icc0
113
        bne             icc0,1,fail
114
        subi.p          gr11,4,gr11
115
        bctrlr.p        1,0
116
        bra             read5
117
done5:
118
 
119
        ; access data and insns in non-cache areas
120
        sethi.p         0x8038,gr11             ; bctrlr 0,0
121
        setlo           0x2000,gr11
122
 
123
        sethi.p         0xff00,gr10             ; documented area
124
        setlo           0x0000,gr10
125
        sti             gr11,@(gr10,0)
126
        jmpl            @(gr10,gr0)
127
 
128
        ;  enable RAM mode
129
        movsg           hsr0,gr10
130
        sethi.p         0x0040,gr12
131
        setlo           0x0000,gr12
132
        or              gr10,gr12,gr10
133
        movgs           gr10,hsr0
134
 
135
        sethi.p         0xfe00,gr10             ; documented area
136
        setlo           0x0400,gr10
137
        sti             gr11,@(gr10,0)
138
        jmpl            @(gr10,gr0)
139
 
140
        sethi.p         0xfe40,gr10             ; documented area
141
        setlo           0x0400,gr10
142
        sti             gr11,@(gr10,0)
143
        dcf             @(gr10,gr0)
144
        jmpl            @(gr10,gr0)
145
 
146
        sethi.p         0x0007,gr10             ; non RAM area
147
        setlo           0x0000,gr10
148
        sti             gr11,@(gr10,0)
149
        jmpl            @(gr10,gr0)
150
 
151
        sethi.p         0xfe00,gr10             ; insn RAM area
152
        setlo           0x0000,gr10
153
        sti             gr11,@(gr10,0)
154
        jmpl            @(gr10,gr0)
155
 
156
        sethi.p         0xfe40,gr10             ; data RAM area
157
        setlo           0x0000,gr10
158
        sti             gr11,@(gr10,0)
159
        dcf             @(gr10,gr0)
160
        jmpl            @(gr10,gr0)
161
 
162
        pass
163
fail:
164
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.