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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [dflags.ms] - Blame information for rev 157

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Line No. Rev Author Line
1 24 jeremybenn 
# mach: crisv3 crisv8 crisv10 crisv32
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# output: 31\n
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; Check that flag settings in the delay slot for a conditional branch do
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; not affect the branch.
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 .include "testutils.inc"
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 start
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 moveq 1,r3
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 moveq 0,r4
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; 8-bit branches.
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 move.d r4,r4
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 bne 0f
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 move.d r3,r3
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 bne 1f
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 move.d r4,r4
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 nop
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0:
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 quit
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1:
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 move.d r3,r3
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 beq 0b
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 move.d r4,r4
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 beq 4f
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 move.d r3,r3
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 nop
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 quit
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4:
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 jump 2f
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 nop
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 .space 1000
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; 16-bit branches
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2:
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 move.d r4,r4
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 bne 0b
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 move.d r3,r3
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 bne 3f
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 move.d r4,r4
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 nop
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 quit
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 .space 1000
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3:
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 move.d r3,r3
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 beq 0b
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 move.d r4,r4
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 beq 4f
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 move.d r3,r3
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 nop
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 quit
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 .space 1000
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4:
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 move.d 0x31,r3
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 dumpr3
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 quit

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