OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [movepcw.ms] - Blame information for rev 438

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# mach: crisv3 crisv8 crisv10
2
# xerror:
3
# output: General register read of PC is not implemented.\nprogram stopped with signal 5.\n
4
 
5
 .include "testutils.inc"
6
 startnostack
7
 setf
8
 test.w pc
9
 quit

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.