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# mach: crisv32
 
 .include "testutils.inc"
 
; Check for various non-arithmetic insns that C and V are not affected
; on v32 (where they were on v10), as the generic tests don't cover
; that; they are cleared before testing.
 
; First, a macro testing that VC are unaffected, not counting previous
; register contents.
 .macro nonvc0 insn op
 move.d $r0,$r3
 setf vc
 .ifnc \insn,swapnwbr
 \insn \op,$r3
 .else
 \insn $r3
 .endif
 bcc 9f
 nop
 bvc 9f
 nop
 move.d $r0,$r3
 clearf vc
 .ifnc \insn,swapnwbr
 \insn \op,$r3
 .else
 \insn $r3
 .endif
 bcs 9f
 nop
 bvc 8f
 nop
9:
 fail
8:
 .endm
 
; Use the above, but initialize the non-parameter operand to a value.
 .macro nonvc1 insn val op
 move.d \val,$r0
 nonvc0 \insn,\op
 .endm
 
; Use the above, iterating over various values.
 .macro nonvc2 insn op
 .irp p,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000
 nonvc1 \insn,\p,\op
 nonvc1 \insn,-\p,\op
 .endr
 .endm
 
 .macro nonvc2q insn op min=-63 max=63
 .if \op >= \min &&&& \op <= \max
 nonvc2 \insn,\op
 .endif
 .endm
 
; The above, for each .b .w .d insn variant.
 .macro nonvcbwd insn op
 .irp s,.b,.w,.d
 nonvc2 \insn\s,\op
 .endr
 .endm
 
; For various insns with register, dword constant and memory operands.
 .macro nonvcitermcd op=[$r4]
 nonvc2 and.d,\op
 nonvc2 move.d,\op
 nonvc2 or.d,\op
 .endm
 
; Similar, for various insns with register, word constant and memory operands.
 .macro nonvcitermcw op=[$r4]
 nonvcitermcd \op
 nonvc2 and.w,\op
 nonvc2 move.w,\op
 nonvc2 or.w,\op
 nonvc2 movs.w,\op
 nonvc2 movu.w,\op
 .endm
 
; Similar, for various insns with register, byte constant and memory operands.
 .macro nonvcitermcb op=[$r4]
 nonvcitermcw \op
 nonvc2 and.b,\op
 nonvc2 move.b,\op
 nonvc2 or.b,\op
 nonvc2 movs.b,\op
 nonvc2 movu.b,\op
 .endm
 
; Similar, for insns with quick constant operands.
 .macro nonvciterq op
 nonvcitermcb \op
 nonvc2 bound.b,\op
 nonvc2q andq,\op,min=-32,max=31
 nonvc2q asrq,\op,min=0,max=31
 nonvc2q lsrq,\op,min=0,max=31
 nonvc2q orq,\op,min=-32,max=31
 nonvc2q moveq,\op,min=-32,max=31
 .endm
 
; Similar, for insns with register operands.
 .macro nonvciterr op
 nonvcitermcb \op
 nonvcbwd bound,\op
 nonvc2 abs,\op
 nonvcbwd asr,\op
 nonvc2 dstep,\op
 nonvcbwd lsr,\op
 nonvcbwd lsl,\op
 nonvc2 lz,\op
 nonvc2 swapnwbr
 nonvc2 xor,\op
 .endm
 
; Test all applicable constant, register and memory variants of a value.
 .macro tst op
; Constants
 .if (\op <= 31 &&&& \op >= -32)
 nonvciterq \op
 .elseif (\op <= 255 &&&& \op >= -128)
 nonvcitermcb \op
 nonvcbwd bound,\op
 .elseif (\op <= 65535 &&&& \op >= -32767)
 nonvcitermcw \op
 nonvc2 bound.w,\op
 nonvc2 bound.d,\op
 .else
 nonvcitermcd \op
 nonvc2 bound.d,\op
 .endif
; Registers
 move.d \op,$r4
 nonvciterr $r4
; Memory
 nonvcitermcb [$r5]
 addq 4,$r5
 .section .rodata
 .dword \op
 .previous
 .endm
 
; As above but negation too.
 .macro tstpm op
 tst \op
 tst -\op
 .endm
 
 
; Set up for the actual test.
 
 start
 move.d c0,$r5
 
 .section .rodata
c0:
 .previous
 
; Finally, test.
 
 .irp x,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000
 tstpm \x
 .endr
 
 pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# mach: crisv32`
2
3			`.include "testutils.inc"`
4
5			`; Check for various non-arithmetic insns that C and V are not affected`
6			`; on v32 (where they were on v10), as the generic tests don't cover`
7			`; that; they are cleared before testing.`
8
9			`; First, a macro testing that VC are unaffected, not counting previous`
10			`; register contents.`
11			`.macro nonvc0 insn op`
12			`move.d $r0,$r3`
13			`setf vc`
14			`.ifnc \insn,swapnwbr`
15			`\insn \op,$r3`
16			`.else`
17			`\insn $r3`
18			`.endif`
19			`bcc 9f`
20			`nop`
21			`bvc 9f`
22			`nop`
23			`move.d $r0,$r3`
24			`clearf vc`
25			`.ifnc \insn,swapnwbr`
26			`\insn \op,$r3`
27			`.else`
28			`\insn $r3`
29			`.endif`
30			`bcs 9f`
31			`nop`
32			`bvc 8f`
33			`nop`
34			`9:`
35			`fail`
36			`8:`
37			`.endm`
38
39			`; Use the above, but initialize the non-parameter operand to a value.`
40			`.macro nonvc1 insn val op`
41			`move.d \val,$r0`
42			`nonvc0 \insn,\op`
43			`.endm`
44
45			`; Use the above, iterating over various values.`
46			`.macro nonvc2 insn op`
47			`.irp p,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000`
48			`nonvc1 \insn,\p,\op`
49			`nonvc1 \insn,-\p,\op`
50			`.endr`
51			`.endm`
52
53			`.macro nonvc2q insn op min=-63 max=63`
54			`.if \op >= \min &&&& \op <= \max`
55			`nonvc2 \insn,\op`
56			`.endif`
57			`.endm`
58
59			`; The above, for each .b .w .d insn variant.`
60			`.macro nonvcbwd insn op`
61			`.irp s,.b,.w,.d`
62			`nonvc2 \insn\s,\op`
63			`.endr`
64			`.endm`
65
66			`; For various insns with register, dword constant and memory operands.`
67			`.macro nonvcitermcd op=[$r4]`
68			`nonvc2 and.d,\op`
69			`nonvc2 move.d,\op`
70			`nonvc2 or.d,\op`
71			`.endm`
72
73			`; Similar, for various insns with register, word constant and memory operands.`
74			`.macro nonvcitermcw op=[$r4]`
75			`nonvcitermcd \op`
76			`nonvc2 and.w,\op`
77			`nonvc2 move.w,\op`
78			`nonvc2 or.w,\op`
79			`nonvc2 movs.w,\op`
80			`nonvc2 movu.w,\op`
81			`.endm`
82
83			`; Similar, for various insns with register, byte constant and memory operands.`
84			`.macro nonvcitermcb op=[$r4]`
85			`nonvcitermcw \op`
86			`nonvc2 and.b,\op`
87			`nonvc2 move.b,\op`
88			`nonvc2 or.b,\op`
89			`nonvc2 movs.b,\op`
90			`nonvc2 movu.b,\op`
91			`.endm`
92
93			`; Similar, for insns with quick constant operands.`
94			`.macro nonvciterq op`
95			`nonvcitermcb \op`
96			`nonvc2 bound.b,\op`
97			`nonvc2q andq,\op,min=-32,max=31`
98			`nonvc2q asrq,\op,min=0,max=31`
99			`nonvc2q lsrq,\op,min=0,max=31`
100			`nonvc2q orq,\op,min=-32,max=31`
101			`nonvc2q moveq,\op,min=-32,max=31`
102			`.endm`
103
104			`; Similar, for insns with register operands.`
105			`.macro nonvciterr op`
106			`nonvcitermcb \op`
107			`nonvcbwd bound,\op`
108			`nonvc2 abs,\op`
109			`nonvcbwd asr,\op`
110			`nonvc2 dstep,\op`
111			`nonvcbwd lsr,\op`
112			`nonvcbwd lsl,\op`
113			`nonvc2 lz,\op`
114			`nonvc2 swapnwbr`
115			`nonvc2 xor,\op`
116			`.endm`
117
118			`; Test all applicable constant, register and memory variants of a value.`
119			`.macro tst op`
120			`; Constants`
121			`.if (\op <= 31 &&&& \op >= -32)`
122			`nonvciterq \op`
123			`.elseif (\op <= 255 &&&& \op >= -128)`
124			`nonvcitermcb \op`
125			`nonvcbwd bound,\op`
126			`.elseif (\op <= 65535 &&&& \op >= -32767)`
127			`nonvcitermcw \op`
128			`nonvc2 bound.w,\op`
129			`nonvc2 bound.d,\op`
130			`.else`
131			`nonvcitermcd \op`
132			`nonvc2 bound.d,\op`
133			`.endif`
134			`; Registers`
135			`move.d \op,$r4`
136			`nonvciterr $r4`
137			`; Memory`
138			`nonvcitermcb [$r5]`
139			`addq 4,$r5`
140			`.section .rodata`
141			`.dword \op`
142			`.previous`
143			`.endm`
144
145			`; As above but negation too.`
146			`.macro tstpm op`
147			`tst \op`
148			`tst -\op`
149			`.endm`
150
151
152			`; Set up for the actual test.`
153
154			`start`
155			`move.d c0,$r5`
156
157			`.section .rodata`
158			`c0:`
159			`.previous`
160
161			`; Finally, test.`
162
163			`.irp x,0,1,2,31,32,63,64,127,128,255,256,32767,32768,65535,65536,0x7fffffff,0x80000000`
164			`tstpm \x`
165			`.endr`
166
167			`pass`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [nonvcv32.ms] - Blame information for rev 438