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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [cris/] [asm/] [tjmpsrv32.ms] - Blame information for rev 157

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Line No. Rev Author Line
1 24 jeremybenn
#mach: crisv32
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#output: Basic clock cycles, total @: 17\n
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#output: Memory source stall cycles: 0\n
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#output: Memory read-after-write stall cycles: 0\n
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#output: Movem source stall cycles: 0\n
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#output: Movem destination stall cycles: 0\n
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#output: Movem address stall cycles: 0\n
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#output: Multiplication source stall cycles: 0\n
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#output: Jump source stall cycles: 5\n
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#output: Branch misprediction stall cycles: 0\n
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#output: Jump target stall cycles: 0\n
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#sim: --cris-cycles=basic
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; Check that "ret"-type insns get the right number of penalty
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; cycles for the special register source.
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 .include "testutils.inc"
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 startnostack
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 move.d 1f,$r1
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 move.d 0f,$r0
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 move $r0,$mof
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 jump $mof      ; 2 cycles penalty.
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 nop
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0:
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 move [$r1],$srp
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 nop
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 ret            ; 1 cycle penalty.
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 nop
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 break 15
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0:
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 move 2f,$nrp
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 nop
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 nop
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 jump $nrp      ; no penalty.
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 nop
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 break 15
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2:
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 move 3f,$srp   ; 2 cycles penalty.
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 ret
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 nop
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3:
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 break 15
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1:
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 .dword 0b

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