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# fr30 testcase for add $Rj,$Ri, add $u4,$Rj
# mach(): fr30
 
        .include "testutils.inc"
 
        START
 
        .text
        .global add
add:
        ; Test add $Rj,$Ri
        mvi_h_gr        1,r7
        mvi_h_gr        2,r8
        set_cc          0x0f            ; Set mask opposite of expected
        add             r7,r8
        test_cc         0 0 0 0
        test_h_gr       3,r8
 
        mvi_h_gr        0x7fffffff,r7
        mvi_h_gr        1,r8
        set_cc          0x05            ; Set mask opposite of expected
        add             r7,r8
        test_cc         1 0 1 0
        test_h_gr       0x80000000,r8
 
        set_cc          0x08            ; Set mask opposite of expected
        add             r8,r8
        test_cc         0 1 1 1
        test_h_gr       0,r8
 
        ; Test add $u4Ri
        mvi_h_gr        4,r8
        set_cc          0x0f            ; Set mask opposite of expected
        add             0,r8
        test_cc         0 0 0 0
        test_h_gr       4,r8
        set_cc          0x0f            ; Set mask opposite of expected
        add             1,r8
        test_cc         0 0 0 0
        test_h_gr       5,r8
        set_cc          0x0f            ; Set mask opposite of expected
        add             15,r8
        test_cc         0 0 0 0
        test_h_gr       20,r8
        mvi_h_gr        0x7fffffff,r8   ; test neg and overflow bits
        set_cc          0x05            ; Set mask opposite of expected
        add             1,r8
        test_cc         1 0 1 0
        test_h_gr       0x80000000,r8
        set_cc          0x08            ; Set mask opposite of expected
        add             r8,r8           ; test zero, carry and overflow bits
        test_cc         0 1 1 1;
        test_h_gr       0,r8
 
        pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# fr30 testcase for add $Rj,$Ri, add $u4,$Rj`
2			`# mach(): fr30`
3
4			`.include "testutils.inc"`
5
6			`START`
7
8			`.text`
9			`.global add`
10			`add:`
11			`; Test add $Rj,$Ri`
12			`mvi_h_gr 1,r7`
13			`mvi_h_gr 2,r8`
14			`set_cc 0x0f ; Set mask opposite of expected`
15			`add r7,r8`
16			`test_cc 0 0 0 0`
17			`test_h_gr 3,r8`
18
19			`mvi_h_gr 0x7fffffff,r7`
20			`mvi_h_gr 1,r8`
21			`set_cc 0x05 ; Set mask opposite of expected`
22			`add r7,r8`
23			`test_cc 1 0 1 0`
24			`test_h_gr 0x80000000,r8`
25
26			`set_cc 0x08 ; Set mask opposite of expected`
27			`add r8,r8`
28			`test_cc 0 1 1 1`
29			`test_h_gr 0,r8`
30
31			`; Test add $u4Ri`
32			`mvi_h_gr 4,r8`
33			`set_cc 0x0f ; Set mask opposite of expected`
34			`add 0,r8`
35			`test_cc 0 0 0 0`
36			`test_h_gr 4,r8`
37			`set_cc 0x0f ; Set mask opposite of expected`
38			`add 1,r8`
39			`test_cc 0 0 0 0`
40			`test_h_gr 5,r8`
41			`set_cc 0x0f ; Set mask opposite of expected`
42			`add 15,r8`
43			`test_cc 0 0 0 0`
44			`test_h_gr 20,r8`
45			`mvi_h_gr 0x7fffffff,r8 ; test neg and overflow bits`
46			`set_cc 0x05 ; Set mask opposite of expected`
47			`add 1,r8`
48			`test_cc 1 0 1 0`
49			`test_h_gr 0x80000000,r8`
50			`set_cc 0x08 ; Set mask opposite of expected`
51			`add r8,r8 ; test zero, carry and overflow bits`
52			`test_cc 0 1 1 1;`
53			`test_h_gr 0,r8`
54
55			`pass`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [add.cgs] - Blame information for rev 301