URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [bandl.cgs] - Blame information for rev 157

Details | Compare with Previous | View Log


# fr30 testcase for bandl $Rj,@$Ri
# mach(): fr30
 
        .include "testutils.inc"
 
        START
 
        .text
        .global bandl
bandl:
        ; Test bandl $Rj,@$Ri
        mvi_h_mem       0x55555555,sp
        set_cc          0x0f            ; Condition codes should not change
        bandl           0x0a,@sp
        test_cc         1 1 1 1
        test_h_mem      0x50555555,sp
 
        mvi_h_mem       0xffffffff,sp
        set_cc          0x04            ; Condition codes should not change
        bandl           0x0a,@sp
        test_cc         0 1 0 0
        test_h_mem      0xfaffffff,sp
 
        mvi_h_mem       0x5effffff,sp
        set_cc          0x0a            ; Condition codes should not change
        bandl           0x07,@sp
        test_cc         1 0 1 0
        test_h_mem      0x56ffffff,sp
 
        pass

Line No.	Rev	Author	Line
1	24	jeremybenn	`# fr30 testcase for bandl $Rj,@$Ri`
2			`# mach(): fr30`
3
4			`.include "testutils.inc"`
5
6			`START`
7
8			`.text`
9			`.global bandl`
10			`bandl:`
11			`; Test bandl $Rj,@$Ri`
12			`mvi_h_mem 0x55555555,sp`
13			`set_cc 0x0f ; Condition codes should not change`
14			`bandl 0x0a,@sp`
15			`test_cc 1 1 1 1`
16			`test_h_mem 0x50555555,sp`
17
18			`mvi_h_mem 0xffffffff,sp`
19			`set_cc 0x04 ; Condition codes should not change`
20			`bandl 0x0a,@sp`
21			`test_cc 0 1 0 0`
22			`test_h_mem 0xfaffffff,sp`
23
24			`mvi_h_mem 0x5effffff,sp`
25			`set_cc 0x0a ; Condition codes should not change`
26			`bandl 0x07,@sp`
27			`test_cc 1 0 1 0`
28			`test_h_mem 0x56ffffff,sp`
29
30			`pass`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [bandl.cgs] - Blame information for rev 157