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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [div1.cgs] - Blame information for rev 157

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Line No. Rev Author Line
1 24 jeremybenn
# fr30 testcase for div1 $Ri
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# mach(): fr30
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        .include "testutils.inc"
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        START
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        .text
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        .global div1
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div1:
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        ; Test div1 $Ri
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        ; example from the manual -- all status bits 0
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        mvi_h_gr        0x00ffffff,r2
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        mvi_h_dr        0x00ffffff,mdh
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        mvi_h_dr        0x00000000,mdl
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        set_dbits       0x0
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        set_cc          0x00
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        div1            r2
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        test_cc         0 0 0 0
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        test_dbits      0x0
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        test_h_gr       0x00ffffff,r2
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        test_h_dr       0x00ffffff,mdh  ; misprinted in manual?
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        test_h_dr       0x00000001,mdl
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        ; D0 == 1
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        set_dbits       0x1
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        set_cc          0x00
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        div1            r2
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        test_cc         0 0 0 0
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        test_dbits      0x1
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        test_h_gr       0x00ffffff,r2
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        test_h_dr       0x01fffffe,mdh
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        test_h_dr       0x00000002,mdl
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        ; D1 == 1
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        set_dbits       0x2
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        set_cc          0x00
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        div1            r2
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        test_cc         0 0 0 0
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        test_dbits      0x2
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        test_h_gr       0x00ffffff,r2
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        test_h_dr       0x03fffffc,mdh
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        test_h_dr       0x00000004,mdl
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        ; D0 == 1, D1 == 1
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        set_dbits       0x3
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        set_cc          0x00
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        div1            r2
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        test_cc         0 0 0 0
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        test_dbits      0x3
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        test_h_gr       0x00ffffff,r2
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        test_h_dr       0x08fffff7,mdh
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        test_h_dr       0x00000009,mdl
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        ; C == 1
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        mvi_h_gr        0x11ffffef,r2
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        set_dbits       0x0
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        set_cc          0x00
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        div1            r2
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        test_cc         0 0 0 1
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        test_dbits      0x0
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        test_h_gr       0x11ffffef,r2
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        test_h_dr       0x11ffffee,mdh
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        test_h_dr       0x00000012,mdl
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        ; D0 == 1, C == 1
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        mvi_h_gr        0x23ffffdd,r2
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        set_dbits       0x1
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        set_cc          0x00
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        div1            r2
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        test_cc         0 0 0 1
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        test_dbits      0x1
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        test_h_gr       0x23ffffdd,r2
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        test_h_dr       0xffffffff,mdh
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        test_h_dr       0x00000025,mdl
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        ; D1 == 1, C == 1
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        mvi_h_gr        0x00000003,r2
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        set_dbits       0x2
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        set_cc          0x00
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        div1            r2
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        test_cc         0 0 0 1
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        test_dbits      0x2
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        test_h_gr       0x00000003,r2
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        test_h_dr       0x00000001,mdh
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        test_h_dr       0x0000004b,mdl
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        ; D0 == 1, D1 == 1, C == 1
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        mvi_h_gr        0xfffffffe,r2
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        set_dbits       0x3
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        set_cc          0x00
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        div1            r2
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        test_cc         0 0 0 1
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        test_dbits      0x3
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        test_h_gr       0xfffffffe,r2
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        test_h_dr       0x00000002,mdh
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        test_h_dr       0x00000096,mdl
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        ; remainder is zero
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        mvi_h_gr        0x00000004,r2
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        set_dbits       0x0
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        set_cc          0x00
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        div1            r2
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        test_cc         0 1 0 0
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        test_dbits      0x0
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        test_h_gr       0x00000004,r2
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        test_h_dr       0x00000000,mdh
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        test_h_dr       0x0000012d,mdl
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        pass
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