OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [dmovb.cgs] - Blame information for rev 205

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# fr30 testcase for dmovb
2
# mach(): fr30
3
 
4
        .include "testutils.inc"
5
        START
6
 
7
        .text
8
        .global dmovb
9
dmovb:
10
        ; Test dmovb @$dir8,$R13
11
        mvi_h_gr        0xdeadbeef,r1
12
        mvi_h_gr        0x80,r2
13
        mvr_h_mem       r1,r2
14
        set_cc          0x0f            ; Condition codes shouldn't change
15
        dmovb           @0x80,r13
16
        test_cc         1 1 1 1
17
        test_h_gr       0xffffffde,r13
18
 
19
        ; Test dmovb $R13,@$dir8
20
        mvi_h_gr        0xbeefdead,r13
21
        set_cc          0x0e            ; Condition codes shouldn't change
22
        dmovb           r13,@0x80
23
        test_cc         1 1 1 0
24
        test_h_mem      0xadadbeef,r2
25
 
26
        ; Test dmovb @$dir8,@R13+
27
        mvi_h_gr        0x7c,r13
28
        mvi_h_mem       0xdeadbeef,r13
29
        set_cc          0x0d            ; Condition codes shouldn't change
30
        dmovb           @0x7f,@r13+
31
        test_cc         1 1 0 1
32
        mvi_h_gr        0x7c,r2
33
        test_h_mem      0xefadbeef,r2
34
        test_h_gr       0x7d,r13
35
 
36
        ; Test dmovb @$R13+,@$dir8
37
        mvi_h_gr        0x7c,r13
38
        mvi_h_mem       0xbeefdead,r13
39
        set_cc          0x0c            ; Condition codes shouldn't change
40
        dmovb           @r13+,@0x7f
41
        test_cc         1 1 0 0
42
        mvi_h_gr        0x7c,r2
43
        test_h_mem      0xbeefdebe,r2
44
        test_h_gr       0x7d,r13
45
 
46
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.