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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [mul.cgs] - Blame information for rev 157

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Line No. Rev Author Line
1 24 jeremybenn
# fr30 testcase for mul $Rj,$Ri
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# mach(): fr30
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        .include "testutils.inc"
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        START
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        .text
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        .global mul
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mul:
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        ; Test mul $Rj,$Ri
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        ; Positive operands
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        mvi_h_gr        3,r7            ; multiply small numbers
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        mvi_h_gr        2,r8
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        set_cc          0x0f            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 0 1
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        test_h_dr       0,mdh
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        test_h_dr       6,mdl
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        mvi_h_gr        1,r7            ; multiply by 1
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        mvi_h_gr        2,r8
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        set_cc          0x0e            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 0 0
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        test_h_dr       0,mdh
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        test_h_dr       2,mdl
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        mvi_h_gr        2,r7            ; multiply by 1
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        mvi_h_gr        1,r8
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        set_cc          0x0f            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 0 1
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        test_h_dr       0,mdh
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        test_h_dr       2,mdl
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        mvi_h_gr        0,r7            ; multiply by 0
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        mvi_h_gr        2,r8
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        set_cc          0x0b            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 1 0 1
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        test_h_dr       0,mdh
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        test_h_dr       0,mdl
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        mvi_h_gr        2,r7            ; multiply by 0
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        mvi_h_gr        0,r8
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        set_cc          0x0a            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 1 0 0
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        test_h_dr       0,mdh
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        test_h_dr       0,mdl
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        mvi_h_gr        0x3fffffff,r7   ; 31 bit result
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        mvi_h_gr        2,r8
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        set_cc          0x0f            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 0 1
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        test_h_dr       0,mdh
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        test_h_dr       0x7ffffffe,mdl
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        mvi_h_gr        0x40000000,r7   ; 32 bit result
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        mvi_h_gr        2,r8
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        set_cc          0x04            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         1 0 1 0
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        test_h_dr       0,mdh
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        test_h_dr       0x80000000,mdl
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        mvi_h_gr        0x40000000,r7   ; 33 bit result
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        mvi_h_gr        4,r8
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        set_cc          0x0d            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 1 1
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        test_h_dr       1,mdh
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        test_h_dr       0x00000000,mdl
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        mvi_h_gr        0x7fffffff,r7   ; max positive result
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        mvi_h_gr        0x7fffffff,r8
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        set_cc          0x0d            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 1 1
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        test_h_dr       0x3fffffff,mdh
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        test_h_dr       0x00000001,mdl
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        ; Mixed operands
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        mvi_h_gr        -3,r7           ; multiply small numbers
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        mvi_h_gr        2,r8
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        set_cc          0x07            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         1 0 0 1
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        test_h_dr       -1,mdh
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        test_h_dr       -6,mdl
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        mvi_h_gr        3,r7            ; multiply small numbers
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        mvi_h_gr        -2,r8
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        set_cc          0x07            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         1 0 0 1
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        test_h_dr       -1,mdh
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        test_h_dr       -6,mdl
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        mvi_h_gr        1,r7            ; multiply by 1
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        mvi_h_gr        -2,r8
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        set_cc          0x06            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         1 0 0 0
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        test_h_dr       -1,mdh
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        test_h_dr       -2,mdl
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        mvi_h_gr        -2,r7           ; multiply by 1
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        mvi_h_gr        1,r8
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        set_cc          0x07            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         1 0 0 1
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        test_h_dr       -1,mdh
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        test_h_dr       -2,mdl
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        mvi_h_gr        0,r7            ; multiply by 0
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        mvi_h_gr        -2,r8
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        set_cc          0x0b            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 1 0 1
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        test_h_dr       0,mdh
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        test_h_dr       0,mdl
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        mvi_h_gr        -2,r7           ; multiply by 0
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        mvi_h_gr        0,r8
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        set_cc          0x0a            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 1 0 0
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        test_h_dr       0,mdh
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        test_h_dr       0,mdl
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        mvi_h_gr        0x20000001,r7   ; 31 bit result
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        mvi_h_gr        -2,r8
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        set_cc          0x07            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         1 0 0 1
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        test_h_dr       0xffffffff,mdh
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        test_h_dr       0xbffffffe,mdl
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        mvi_h_gr        0x40000000,r7   ; 32 bit result
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        mvi_h_gr        -2,r8
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        set_cc          0x06            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         1 0 0 0
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        test_h_dr       0xffffffff,mdh
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        test_h_dr       0x80000000,mdl
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        mvi_h_gr        0x40000001,r7   ; 32 bit result
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        mvi_h_gr        -2,r8
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        set_cc          0x0c            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 1 0
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        test_h_dr       0xffffffff,mdh
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        test_h_dr       0x7ffffffe,mdl
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        mvi_h_gr        0x40000000,r7   ; 33 bit result
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        mvi_h_gr        -4,r8
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        set_cc          0x0d            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 1 1
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        test_h_dr       0xffffffff,mdh
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        test_h_dr       0x00000000,mdl
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        mvi_h_gr        0x7fffffff,r7   ; max negative result
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        mvi_h_gr        0x80000000,r8
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        set_cc          0x05            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         1 0 1 1
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        test_h_dr       0xc0000000,mdh
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        test_h_dr       0x80000000,mdl
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        ; Negative operands
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        mvi_h_gr        -3,r7           ; multiply small numbers
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        mvi_h_gr        -2,r8
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        set_cc          0x0f            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 0 1
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        test_h_dr       0,mdh
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        test_h_dr       6,mdl
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        mvi_h_gr        -1,r7           ; multiply by 1
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        mvi_h_gr        -2,r8
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        set_cc          0x0e            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 0 0
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        test_h_dr       0,mdh
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        test_h_dr       2,mdl
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        mvi_h_gr        -2,r7           ; multiply by 1
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        mvi_h_gr        -1,r8
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        set_cc          0x0f            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 0 1
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        test_h_dr       0,mdh
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        test_h_dr       2,mdl
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        mvi_h_gr        0xc0000001,r7   ; 31 bit result
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        mvi_h_gr        -2,r8
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        set_cc          0x0f            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 0 1
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        test_h_dr       0,mdh
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        test_h_dr       0x7ffffffe,mdl
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        mvi_h_gr        0xc0000000,r7   ; 32 bit result
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        mvi_h_gr        -2,r8
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        set_cc          0x04            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         1 0 1 0
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        test_h_dr       0,mdh
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        test_h_dr       0x80000000,mdl
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        mvi_h_gr        0xc0000000,r7   ; 33 bit result
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        mvi_h_gr        -4,r8
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        set_cc          0x0d            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 1 1
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        test_h_dr       1,mdh
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        test_h_dr       0x00000000,mdl
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        mvi_h_gr        0x80000001,r7   ; almost max positive result
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        mvi_h_gr        0x80000001,r8
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        set_cc          0x0d            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 1 1
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        test_h_dr       0x3fffffff,mdh
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        test_h_dr       0x00000001,mdl
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        mvi_h_gr        0x80000000,r7   ; max positive result
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        mvi_h_gr        0x80000000,r8
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        set_cc          0x0d            ; Set mask opposite of expected
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        mul             r7,r8
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        test_cc         0 0 1 1
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        test_h_dr       0x40000000,mdh
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        test_h_dr       0x00000000,mdl
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        pass

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