URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [mulh.cgs] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log


# fr30 testcase for mulh $Rj,$Ri
# mach(): fr30
 
        .include "testutils.inc"
 
        START
 
        .text
        .global mulh
mulh:
        ; Test mulh $Rj,$Ri
        ; Positive operands
        mvi_h_gr        0xdead0003,r7           ; multiply small numbers
        mvi_h_gr        0xbeef0002,r8
        set_cc          0x09            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 1
        test_h_dr       6,mdl
 
        mvi_h_gr        0xdead0001,r7           ; multiply by 1
        mvi_h_gr        0xbeef0002,r8
        set_cc          0x08            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 0
        test_h_dr       2,mdl
 
        mvi_h_gr        0xdead0002,r7           ; multiply by 1
        mvi_h_gr        0xbeef0001,r8
        set_cc          0x09            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 1
        test_h_dr       2,mdl
 
        mvi_h_gr        0xdead0000,r7           ; multiply by 0
        mvi_h_gr        0xbeef0002,r8
        set_cc          0x09            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 1
        test_h_dr       0,mdl
 
        mvi_h_gr        0xdead0002,r7           ; multiply by 0
        mvi_h_gr        0xbeef0000,r8
        set_cc          0x08            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 0
        test_h_dr       0,mdl
 
        mvi_h_gr        0xdead3fff,r7   ; 15 bit result
        mvi_h_gr        0xbeef0002,r8
        set_cc          0x09            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 1
        test_h_dr       0x00007ffe,mdl
 
        mvi_h_gr        0xdead4000,r7   ; 16 bit result
        mvi_h_gr        0xbeef0002,r8
        set_cc          0x0a            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 1 0
        test_h_dr       0x00008000,mdl
 
        mvi_h_gr        0xdead4000,r7   ; 17 bit result
        mvi_h_gr        0xbeef0004,r8
        set_cc          0x0b            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 1 1
        test_h_dr       0x00010000,mdl
 
        mvi_h_gr        0xdead7fff,r7   ; max positive result
        mvi_h_gr        0xbeef7fff,r8
        set_cc          0x0b            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 1 1
        test_h_dr       0x3fff0001,mdl
 
        ; Mixed operands
        mvi_h_gr        -3,r7           ; multiply small numbers
        mvi_h_gr        2,r8
        set_cc          0x05            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         1 0 0 1
        test_h_dr       -6,mdl
 
        mvi_h_gr        3,r7            ; multiply small numbers
        mvi_h_gr        -2,r8
        set_cc          0x05            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         1 0 0 1
        test_h_dr       -6,mdl
 
        mvi_h_gr        1,r7            ; multiply by 1
        mvi_h_gr        -2,r8
        set_cc          0x04            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         1 0 0 0
        test_h_dr       -2,mdl
 
        mvi_h_gr        -2,r7           ; multiply by 1
        mvi_h_gr        1,r8
        set_cc          0x05            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         1 0 0 1
        test_h_dr       -2,mdl
 
        mvi_h_gr        0,r7            ; multiply by 0
        mvi_h_gr        -2,r8
        set_cc          0x09            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 1
        test_h_dr       0,mdl
 
        mvi_h_gr        -2,r7           ; multiply by 0
        mvi_h_gr        0,r8
        set_cc          0x08            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 0
        test_h_dr       0,mdl
 
        mvi_h_gr        0xdead2001,r7   ; 15 bit result
        mvi_h_gr        -2,r8
        set_cc          0x05            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         1 0 0 1
        test_h_dr       0xffffbffe,mdl
 
        mvi_h_gr        0xdead4000,r7   ; 16 bit result
        mvi_h_gr        -2,r8
        set_cc          0x04            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         1 0 0 0
        test_h_dr       0xffff8000,mdl
 
        mvi_h_gr        0xdead4001,r7   ; 16 bit result
        mvi_h_gr        -2,r8
        set_cc          0x06            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         1 0 1 0
        test_h_dr       0xffff7ffe,mdl
 
        mvi_h_gr        0xdead4000,r7   ; 17 bit result
        mvi_h_gr        -4,r8
        set_cc          0x07            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         1 0 1 1
        test_h_dr       0xffff0000,mdl
 
        mvi_h_gr        0xdead7fff,r7   ; max negative result
        mvi_h_gr        0xbeef8000,r8
        set_cc          0x07            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         1 0 1 1
        test_h_dr       0xc0008000,mdl
 
        ; Negative operands
        mvi_h_gr        -3,r7           ; multiply small numbers
        mvi_h_gr        -2,r8
        set_cc          0x09            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 1
        test_h_dr       6,mdl
 
        mvi_h_gr        -1,r7           ; multiply by 1
        mvi_h_gr        -2,r8
        set_cc          0x08            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 0
        test_h_dr       2,mdl
 
        mvi_h_gr        -2,r7           ; multiply by 1
        mvi_h_gr        -1,r8
        set_cc          0x09            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 1
        test_h_dr       2,mdl
 
        mvi_h_gr        0xdeadc001,r7   ; 15 bit result
        mvi_h_gr        -2,r8
        set_cc          0x09            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 0 1
        test_h_dr       0x00007ffe,mdl
 
        mvi_h_gr        0xdeadc000,r7   ; 16 bit result
        mvi_h_gr        -2,r8
        set_cc          0x0a            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 1 0
        test_h_dr       0x00008000,mdl
 
        mvi_h_gr        0xdeadc000,r7   ; 17 bit result
        mvi_h_gr        -4,r8
        set_cc          0x0b            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 1 1
        test_h_dr       0x00010000,mdl
 
        mvi_h_gr        0xdead8001,r7   ; almost max positive result
        mvi_h_gr        0xbeef8001,r8
        set_cc          0x0b            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 1 1
        test_h_dr       0x3fff0001,mdl
 
        mvi_h_gr        0xdead8000,r7   ; max positive result
        mvi_h_gr        0xbeef8000,r8
        set_cc          0x0b            ; Set mask opposite of expected
        mulh            r7,r8
        test_cc         0 1 1 1
        test_h_dr       0x40000000,mdl
 
        pass

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [mulh.cgs] - Blame information for rev 24

Line No.	Rev	Author	Line
1	24	jeremybenn	`# fr30 testcase for mulh $Rj,$Ri`
2			`# mach(): fr30`
3
4			`.include "testutils.inc"`
5
6			`START`
7
8			`.text`
9			`.global mulh`
10			`mulh:`
11			`; Test mulh $Rj,$Ri`
12			`; Positive operands`
13			`mvi_h_gr 0xdead0003,r7 ; multiply small numbers`
14			`mvi_h_gr 0xbeef0002,r8`
15			`set_cc 0x09 ; Set mask opposite of expected`
16			`mulh r7,r8`
17			`test_cc 0 1 0 1`
18			`test_h_dr 6,mdl`
19
20			`mvi_h_gr 0xdead0001,r7 ; multiply by 1`
21			`mvi_h_gr 0xbeef0002,r8`
22			`set_cc 0x08 ; Set mask opposite of expected`
23			`mulh r7,r8`
24			`test_cc 0 1 0 0`
25			`test_h_dr 2,mdl`
26
27			`mvi_h_gr 0xdead0002,r7 ; multiply by 1`
28			`mvi_h_gr 0xbeef0001,r8`
29			`set_cc 0x09 ; Set mask opposite of expected`
30			`mulh r7,r8`
31			`test_cc 0 1 0 1`
32			`test_h_dr 2,mdl`
33
34			`mvi_h_gr 0xdead0000,r7 ; multiply by 0`
35			`mvi_h_gr 0xbeef0002,r8`
36			`set_cc 0x09 ; Set mask opposite of expected`
37			`mulh r7,r8`
38			`test_cc 0 1 0 1`
39			`test_h_dr 0,mdl`
40
41			`mvi_h_gr 0xdead0002,r7 ; multiply by 0`
42			`mvi_h_gr 0xbeef0000,r8`
43			`set_cc 0x08 ; Set mask opposite of expected`
44			`mulh r7,r8`
45			`test_cc 0 1 0 0`
46			`test_h_dr 0,mdl`
47
48			`mvi_h_gr 0xdead3fff,r7 ; 15 bit result`
49			`mvi_h_gr 0xbeef0002,r8`
50			`set_cc 0x09 ; Set mask opposite of expected`
51			`mulh r7,r8`
52			`test_cc 0 1 0 1`
53			`test_h_dr 0x00007ffe,mdl`
54
55			`mvi_h_gr 0xdead4000,r7 ; 16 bit result`
56			`mvi_h_gr 0xbeef0002,r8`
57			`set_cc 0x0a ; Set mask opposite of expected`
58			`mulh r7,r8`
59			`test_cc 0 1 1 0`
60			`test_h_dr 0x00008000,mdl`
61
62			`mvi_h_gr 0xdead4000,r7 ; 17 bit result`
63			`mvi_h_gr 0xbeef0004,r8`
64			`set_cc 0x0b ; Set mask opposite of expected`
65			`mulh r7,r8`
66			`test_cc 0 1 1 1`
67			`test_h_dr 0x00010000,mdl`
68
69			`mvi_h_gr 0xdead7fff,r7 ; max positive result`
70			`mvi_h_gr 0xbeef7fff,r8`
71			`set_cc 0x0b ; Set mask opposite of expected`
72			`mulh r7,r8`
73			`test_cc 0 1 1 1`
74			`test_h_dr 0x3fff0001,mdl`
75
76			`; Mixed operands`
77			`mvi_h_gr -3,r7 ; multiply small numbers`
78			`mvi_h_gr 2,r8`
79			`set_cc 0x05 ; Set mask opposite of expected`
80			`mulh r7,r8`
81			`test_cc 1 0 0 1`
82			`test_h_dr -6,mdl`
83
84			`mvi_h_gr 3,r7 ; multiply small numbers`
85			`mvi_h_gr -2,r8`
86			`set_cc 0x05 ; Set mask opposite of expected`
87			`mulh r7,r8`
88			`test_cc 1 0 0 1`
89			`test_h_dr -6,mdl`
90
91			`mvi_h_gr 1,r7 ; multiply by 1`
92			`mvi_h_gr -2,r8`
93			`set_cc 0x04 ; Set mask opposite of expected`
94			`mulh r7,r8`
95			`test_cc 1 0 0 0`
96			`test_h_dr -2,mdl`
97
98			`mvi_h_gr -2,r7 ; multiply by 1`
99			`mvi_h_gr 1,r8`
100			`set_cc 0x05 ; Set mask opposite of expected`
101			`mulh r7,r8`
102			`test_cc 1 0 0 1`
103			`test_h_dr -2,mdl`
104
105			`mvi_h_gr 0,r7 ; multiply by 0`
106			`mvi_h_gr -2,r8`
107			`set_cc 0x09 ; Set mask opposite of expected`
108			`mulh r7,r8`
109			`test_cc 0 1 0 1`
110			`test_h_dr 0,mdl`
111
112			`mvi_h_gr -2,r7 ; multiply by 0`
113			`mvi_h_gr 0,r8`
114			`set_cc 0x08 ; Set mask opposite of expected`
115			`mulh r7,r8`
116			`test_cc 0 1 0 0`
117			`test_h_dr 0,mdl`
118
119			`mvi_h_gr 0xdead2001,r7 ; 15 bit result`
120			`mvi_h_gr -2,r8`
121			`set_cc 0x05 ; Set mask opposite of expected`
122			`mulh r7,r8`
123			`test_cc 1 0 0 1`
124			`test_h_dr 0xffffbffe,mdl`
125
126			`mvi_h_gr 0xdead4000,r7 ; 16 bit result`
127			`mvi_h_gr -2,r8`
128			`set_cc 0x04 ; Set mask opposite of expected`
129			`mulh r7,r8`
130			`test_cc 1 0 0 0`
131			`test_h_dr 0xffff8000,mdl`
132
133			`mvi_h_gr 0xdead4001,r7 ; 16 bit result`
134			`mvi_h_gr -2,r8`
135			`set_cc 0x06 ; Set mask opposite of expected`
136			`mulh r7,r8`
137			`test_cc 1 0 1 0`
138			`test_h_dr 0xffff7ffe,mdl`
139
140			`mvi_h_gr 0xdead4000,r7 ; 17 bit result`
141			`mvi_h_gr -4,r8`
142			`set_cc 0x07 ; Set mask opposite of expected`
143			`mulh r7,r8`
144			`test_cc 1 0 1 1`
145			`test_h_dr 0xffff0000,mdl`
146
147			`mvi_h_gr 0xdead7fff,r7 ; max negative result`
148			`mvi_h_gr 0xbeef8000,r8`
149			`set_cc 0x07 ; Set mask opposite of expected`
150			`mulh r7,r8`
151			`test_cc 1 0 1 1`
152			`test_h_dr 0xc0008000,mdl`
153
154			`; Negative operands`
155			`mvi_h_gr -3,r7 ; multiply small numbers`
156			`mvi_h_gr -2,r8`
157			`set_cc 0x09 ; Set mask opposite of expected`
158			`mulh r7,r8`
159			`test_cc 0 1 0 1`
160			`test_h_dr 6,mdl`
161
162			`mvi_h_gr -1,r7 ; multiply by 1`
163			`mvi_h_gr -2,r8`
164			`set_cc 0x08 ; Set mask opposite of expected`
165			`mulh r7,r8`
166			`test_cc 0 1 0 0`
167			`test_h_dr 2,mdl`
168
169			`mvi_h_gr -2,r7 ; multiply by 1`
170			`mvi_h_gr -1,r8`
171			`set_cc 0x09 ; Set mask opposite of expected`
172			`mulh r7,r8`
173			`test_cc 0 1 0 1`
174			`test_h_dr 2,mdl`
175
176			`mvi_h_gr 0xdeadc001,r7 ; 15 bit result`
177			`mvi_h_gr -2,r8`
178			`set_cc 0x09 ; Set mask opposite of expected`
179			`mulh r7,r8`
180			`test_cc 0 1 0 1`
181			`test_h_dr 0x00007ffe,mdl`
182
183			`mvi_h_gr 0xdeadc000,r7 ; 16 bit result`
184			`mvi_h_gr -2,r8`
185			`set_cc 0x0a ; Set mask opposite of expected`
186			`mulh r7,r8`
187			`test_cc 0 1 1 0`
188			`test_h_dr 0x00008000,mdl`
189
190			`mvi_h_gr 0xdeadc000,r7 ; 17 bit result`
191			`mvi_h_gr -4,r8`
192			`set_cc 0x0b ; Set mask opposite of expected`
193			`mulh r7,r8`
194			`test_cc 0 1 1 1`
195			`test_h_dr 0x00010000,mdl`
196
197			`mvi_h_gr 0xdead8001,r7 ; almost max positive result`
198			`mvi_h_gr 0xbeef8001,r8`
199			`set_cc 0x0b ; Set mask opposite of expected`
200			`mulh r7,r8`
201			`test_cc 0 1 1 1`
202			`test_h_dr 0x3fff0001,mdl`
203
204			`mvi_h_gr 0xdead8000,r7 ; max positive result`
205			`mvi_h_gr 0xbeef8000,r8`
206			`set_cc 0x0b ; Set mask opposite of expected`
207			`mulh r7,r8`
208			`test_cc 0 1 1 1`
209			`test_h_dr 0x40000000,mdl`
210
211			`pass`