OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [fr30/] [stm1.cgs] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
# fr30 testcase for stm1 ($reglist_low)
2 
# mach(): fr30
3 
 
4 
        .include "testutils.inc"
5 
 
6 
        START
7 
 
8 
        .text
9 
        .global stm1
10 
stm1:
11 
        ; Test stm1 ($reglist_low)
12 
        mvr_h_gr        sp,r1           ; save stack pointer temporarily
13 
        mvr_h_gr        sp,r2           ; save stack pointer permanently
14 
        mvi_h_gr        8,r8
15 
        mvi_h_gr        9,r9
16 
        mvi_h_gr        10,r10
17 
        mvi_h_gr        11,r11
18 
        mvi_h_gr        12,r12
19 
        mvi_h_gr        13,r13
20 
        mvi_h_gr        14,r14
21 
        set_cc          0x0f            ; Condition codes should not change
22 
        stm1            (r8,r10,r12,r14)
23 
        test_cc         1 1 1 1
24 
        inci_h_gr       -4,r1
25 
        test_h_mem      14,r1
26 
        inci_h_gr       -4,r1
27 
        test_h_mem      12,r1
28 
        inci_h_gr       -4,r1
29 
        test_h_mem      10,r1
30 
        inci_h_gr       -4,r1
31 
        testr_h_mem     8,r1
32 
 
33 
        mvr_h_gr        r2,sp           ; restore stack pointer
34 
        mvr_h_gr        r2,r1           ; save stack pointer temporarily
35 
        mvi_h_gr        8,r8
36 
        mvi_h_gr        9,r9
37 
        mvi_h_gr        10,r10
38 
        mvi_h_gr        11,r11
39 
        mvi_h_gr        12,r12
40 
        mvi_h_gr        13,r13
41 
        mvi_h_gr        14,r14
42 
        set_cc          0x0f            ; Condition codes should not change
43 
        stm1            (r9,r11,r13,r15)
44 
        test_cc         1 1 1 1
45 
        inci_h_gr       -4,r1
46 
        testr_h_mem     r2,r1
47 
        inci_h_gr       -4,r1
48 
        test_h_mem      13,r1
49 
        inci_h_gr       -4,r1
50 
        test_h_mem      11,r1
51 
        inci_h_gr       -4,r1
52 
        test_h_mem      9,r1            ; saved r15 is from before stm1
53 
 
54 
        mvr_h_gr        r2,sp           ; restore stack pointer
55 
        mvr_h_gr        r2,r1           ; save stack pointer temporarily
56 
        mvi_h_gr        8,r8
57 
        mvi_h_gr        9,r9
58 
        mvi_h_gr        10,r10
59 
        mvi_h_gr        11,r11
60 
        mvi_h_gr        12,r12
61 
        mvi_h_gr        13,r13
62 
        mvi_h_gr        14,r14
63 
        set_cc          0x0f            ; Condition codes should not change
64 
        stm1            (r9,r13,r15,r11); Order specified should not matter
65 
        test_cc         1 1 1 1
66 
        inci_h_gr       -4,r1
67 
        testr_h_mem     r2,r1
68 
        inci_h_gr       -4,r1
69 
        test_h_mem      13,r1
70 
        inci_h_gr       -4,r1
71 
        test_h_mem      11,r1
72 
        inci_h_gr       -4,r1
73 
        test_h_mem      9,r1            ; saved r15 is from before stm1
74 
 
75 
        mvr_h_gr        r2,sp           ; restore stack pointer
76 
        mvr_h_gr        r2,r1           ; save stack pointer temporarily
77 
        mvi_h_gr        9,r8
78 
        mvi_h_gr        9,r9
79 
        mvi_h_gr        9,r10
80 
        mvi_h_gr        9,r11
81 
        mvi_h_gr        9,r12
82 
        mvi_h_gr        9,r13
83 
        mvi_h_gr        9,r14
84 
        set_cc          0x0f            ; Condition codes should not change
85 
        stm1            ()              ; should do nothing
86 
        test_cc         1 1 1 1
87 
        testr_h_gr      r2,sp
88 
        inci_h_gr       -4,r1
89 
        testr_h_mem     r2,r1
90 
        inci_h_gr       -4,r1
91 
        test_h_mem      13,r1
92 
        inci_h_gr       -4,r1
93 
        test_h_mem      11,r1
94 
        inci_h_gr       -4,r1
95 
        test_h_mem      9,r1
96 
 
97 
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.