OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [addcc.cgs] - Blame information for rev 157

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# frv testcase for addcc $GRi,$GRj,$GRk,$ICCi_1
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global addcc
9
addcc:
10
        set_gr_immed    1,gr7
11
        set_gr_immed    2,gr8
12
        set_icc         0x0f,0          ; Set mask opposite of expected
13
        addcc           gr7,gr8,gr8,icc0
14
        test_icc        0 0 0 0 icc0
15
        test_gr_immed   3,gr8
16
 
17
        set_gr_limmed   0x7fff,0xffff,gr7
18
        set_gr_immed    1,gr8
19
        set_icc         0x05,0          ; Set mask opposite of expected
20
        addcc           gr7,gr8,gr8,icc0
21
        test_icc        1 0 1 0 icc0
22
        test_gr_limmed  0x8000,0x0000,gr8
23
 
24
        set_icc         0x08,0          ; Set mask opposite of expected
25
        addcc           gr8,gr8,gr8,icc0
26
        test_icc        0 1 1 1 icc0
27
        test_gr_immed   0,gr8
28
 
29
        set_gr_limmed   0x8000,0x0000,gr8
30
        set_icc         0x08,0          ; Set mask opposite of expected
31
        addcc           gr8,gr8,gr8,icc0; test zero, carry and overflow bits
32
        test_icc        0 1 1 1 icc0
33
        test_gr_immed   0,gr8
34
 
35
 
36
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.