OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [bltlr.cgs] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
# frv testcase for bltlr $ICCi,$hint
2 
# mach: all
3 
 
4 
        .include "testutils.inc"
5 
 
6 
        start
7 
 
8 
        .global bltlr
9 
bltlr:
10 
        set_spr_addr    bad,lr
11 
        set_icc         0x0 0
12 
        bltlr           icc0,0
13 
 
14 
        set_spr_addr    bad,lr
15 
        set_icc         0x1 1
16 
        bltlr           icc1,1
17 
 
18 
        set_spr_addr    ok3,lr
19 
        set_icc         0x2 2
20 
        bltlr           icc2,2
21 
        fail
22 
ok3:
23 
        set_spr_addr    ok4,lr
24 
        set_icc         0x3 3
25 
        bltlr           icc3,3
26 
        fail
27 
ok4:
28 
        set_spr_addr    bad,lr
29 
        set_icc         0x4 0
30 
        bltlr           icc0,0
31 
 
32 
        set_spr_addr    bad,lr
33 
        set_icc         0x5 1
34 
        bltlr           icc1,1
35 
 
36 
        set_spr_addr    ok7,lr
37 
        set_icc         0x6 2
38 
        bltlr           icc2,2
39 
        fail
40 
ok7:
41 
        set_spr_addr    ok8,lr
42 
        set_icc         0x7 3
43 
        bltlr           icc3,3
44 
        fail
45 
ok8:
46 
        set_spr_addr    ok9,lr
47 
        set_icc         0x8 0
48 
        bltlr           icc0,0
49 
        fail
50 
ok9:
51 
        set_spr_addr    oka,lr
52 
        set_icc         0x9 1
53 
        bltlr           icc1,1
54 
        fail
55 
oka:
56 
        set_spr_addr    bad,lr
57 
        set_icc         0xa 2
58 
        bltlr           icc2,2
59 
 
60 
        set_spr_addr    bad,lr
61 
        set_icc         0xb 3
62 
        bltlr           icc3,3
63 
 
64 
        set_spr_addr    okd,lr
65 
        set_icc         0xc 0
66 
        bltlr           icc0,0
67 
        fail
68 
okd:
69 
        set_spr_addr    oke,lr
70 
        set_icc         0xd 1
71 
        bltlr           icc1,1
72 
        fail
73 
oke:
74 
        set_spr_addr    bad,lr
75 
        set_icc         0xe 2
76 
        bltlr           icc2,2
77 
 
78 
        set_spr_addr    bad,lr
79 
        set_icc         0xf 3
80 
        bltlr           icc3,3
81 
 
82 
        pass
83 
bad:
84 
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.