OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [cmaddhus.cgs] - Blame information for rev 157

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# frv testcase for cmaddhus $FRi,$FRj,$FRj,$CCi,$cond
2
# mach: frv fr500 fr400
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global cmaddhus
9
cmaddhus:
10
        set_spr_immed   0x1b1b,cccr
11
 
12
        set_fr_iimmed   0x0000,0x0000,fr10
13
        set_fr_iimmed   0x0000,0x0000,fr11
14
        cmaddhus        fr10,fr11,fr12,cc0,1
15
        test_fr_limmed  0x0000,0x0000,fr12
16
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
17
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
18
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
19
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
20
 
21
        set_fr_iimmed   0xdead,0x0000,fr10
22
        set_fr_iimmed   0x0000,0xbeef,fr11
23
        cmaddhus        fr10,fr11,fr12,cc0,1
24
        test_fr_limmed  0xdead,0xbeef,fr12
25
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
26
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
27
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
28
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
29
 
30
        set_fr_iimmed   0x0000,0xdead,fr10
31
        set_fr_iimmed   0xbeef,0x0000,fr11
32
        cmaddhus        fr10,fr11,fr12,cc0,1
33
        test_fr_limmed  0xbeef,0xdead,fr12
34
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
35
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
36
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
37
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
38
 
39
        set_fr_iimmed   0x1234,0x5678,fr10
40
        set_fr_iimmed   0x1111,0x1111,fr11
41
        cmaddhus        fr10,fr11,fr12,cc0,1
42
        test_fr_limmed  0x2345,0x6789,fr12
43
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
44
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
45
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
46
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
47
 
48
        set_fr_iimmed   0x7ffe,0x7ffe,fr10
49
        set_fr_iimmed   0x0002,0x0001,fr11
50
        cmaddhus        fr10,fr11,fr12,cc4,1
51
        test_fr_limmed  0x8000,0x7fff,fr12
52
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
53
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
54
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
55
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
56
 
57
        set_fr_iimmed   0xfffe,0xfffe,fr10
58
        set_fr_iimmed   0x0001,0x0002,fr11
59
        cmaddhus        fr10,fr11,fr12,cc4,1
60
        test_fr_limmed  0xffff,0xffff,fr12
61
        test_spr_bits   0x3c,2,4,msr0           ; msr0.sie is set
62
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
63
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
64
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
65
 
66
        set_spr_immed   0,msr0
67
        set_fr_iimmed   0x0002,0x0001,fr10
68
        set_fr_iimmed   0xfffe,0xfffe,fr11
69
        cmaddhus        fr10,fr11,fr12,cc4,1
70
        test_fr_limmed  0xffff,0xffff,fr12
71
        test_spr_bits   0x3c,2,8,msr0           ; msr0.sie is set
72
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
73
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
74
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
75
 
76
        set_spr_immed   0,msr0
77
        set_spr_immed   0,msr1
78
        set_fr_iimmed   0x0001,0x0001,fr10
79
        set_fr_iimmed   0x8000,0x8000,fr11
80
        cmaddhus.p      fr10,fr10,fr12,cc4,1
81
        cmaddhus        fr11,fr11,fr13,cc4,1
82
        test_fr_limmed  0x0002,0x0002,fr12
83
        test_fr_limmed  0xffff,0xffff,fr13
84
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
85
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
86
        test_spr_bits   0x3c,2,0xc,msr1         ; msr1.sie is set
87
        test_spr_bits   2,1,1,msr1              ; msr1.ovf set
88
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
89
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
90
 
91
        set_spr_immed   0,msr0
92
        set_spr_immed   0,msr1
93
        set_fr_iimmed   0x0000,0x0000,fr10
94
        set_fr_iimmed   0x0000,0x0000,fr11
95
        cmaddhus        fr10,fr11,fr12,cc1,0
96
        test_fr_limmed  0x0000,0x0000,fr12
97
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
98
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
99
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
100
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
101
 
102
        set_fr_iimmed   0xdead,0x0000,fr10
103
        set_fr_iimmed   0x0000,0xbeef,fr11
104
        cmaddhus        fr10,fr11,fr12,cc1,0
105
        test_fr_limmed  0xdead,0xbeef,fr12
106
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
107
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
108
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
109
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
110
 
111
        set_fr_iimmed   0x0000,0xdead,fr10
112
        set_fr_iimmed   0xbeef,0x0000,fr11
113
        cmaddhus        fr10,fr11,fr12,cc1,0
114
        test_fr_limmed  0xbeef,0xdead,fr12
115
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
116
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
117
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
118
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
119
 
120
        set_fr_iimmed   0x1234,0x5678,fr10
121
        set_fr_iimmed   0x1111,0x1111,fr11
122
        cmaddhus        fr10,fr11,fr12,cc1,0
123
        test_fr_limmed  0x2345,0x6789,fr12
124
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
125
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
126
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
127
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
128
 
129
        set_fr_iimmed   0x7ffe,0x7ffe,fr10
130
        set_fr_iimmed   0x0002,0x0001,fr11
131
        cmaddhus        fr10,fr11,fr12,cc5,0
132
        test_fr_limmed  0x8000,0x7fff,fr12
133
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
134
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
135
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
136
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
137
 
138
        set_fr_iimmed   0xfffe,0xfffe,fr10
139
        set_fr_iimmed   0x0001,0x0002,fr11
140
        cmaddhus        fr10,fr11,fr12,cc5,0
141
        test_fr_limmed  0xffff,0xffff,fr12
142
        test_spr_bits   0x3c,2,4,msr0           ; msr0.sie is set
143
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
144
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
145
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
146
 
147
        set_spr_immed   0,msr0
148
        set_fr_iimmed   0x0002,0x0001,fr10
149
        set_fr_iimmed   0xfffe,0xfffe,fr11
150
        cmaddhus        fr10,fr11,fr12,cc5,0
151
        test_fr_limmed  0xffff,0xffff,fr12
152
        test_spr_bits   0x3c,2,8,msr0           ; msr0.sie is set
153
        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
154
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
155
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
156
 
157
        set_spr_immed   0,msr0
158
        set_spr_immed   0,msr1
159
        set_fr_iimmed   0x0001,0x0001,fr10
160
        set_fr_iimmed   0x8000,0x8000,fr11
161
        cmaddhus.p      fr10,fr10,fr12,cc5,0
162
        cmaddhus        fr11,fr11,fr13,cc5,0
163
        test_fr_limmed  0x0002,0x0002,fr12
164
        test_fr_limmed  0xffff,0xffff,fr13
165
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
166
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
167
        test_spr_bits   0x3c,2,0xc,msr1         ; msr1.sie is set
168
        test_spr_bits   2,1,1,msr1              ; msr1.ovf set
169
        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
170
        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
171
 
172
        set_fr_iimmed   0xdead,0xbeef,fr12
173
        set_spr_immed   0,msr0
174
        set_spr_immed   0,msr1
175
        set_fr_iimmed   0x0000,0x0000,fr10
176
        set_fr_iimmed   0x0000,0x0000,fr11
177
        cmaddhus        fr10,fr11,fr12,cc0,0
178
        test_fr_limmed  0xdead,0xbeef,fr12
179
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
180
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
181
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
182
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
183
 
184
        set_fr_iimmed   0xbeef,0x0000,fr10
185
        set_fr_iimmed   0x0000,0xdead,fr11
186
        cmaddhus        fr10,fr11,fr12,cc0,0
187
        test_fr_limmed  0xdead,0xbeef,fr12
188
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
189
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
190
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
191
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
192
 
193
        set_fr_iimmed   0x0000,0xdead,fr10
194
        set_fr_iimmed   0xbeef,0x0000,fr11
195
        cmaddhus        fr10,fr11,fr12,cc0,0
196
        test_fr_limmed  0xdead,0xbeef,fr12
197
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
198
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
199
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
200
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
201
 
202
        set_fr_iimmed   0x1234,0x5678,fr10
203
        set_fr_iimmed   0x1111,0x1111,fr11
204
        cmaddhus        fr10,fr11,fr12,cc0,0
205
        test_fr_limmed  0xdead,0xbeef,fr12
206
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
207
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
208
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
209
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
210
 
211
        set_fr_iimmed   0x7ffe,0x7ffe,fr10
212
        set_fr_iimmed   0x0002,0x0001,fr11
213
        cmaddhus        fr10,fr11,fr12,cc4,0
214
        test_fr_limmed  0xdead,0xbeef,fr12
215
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
216
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
217
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
218
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
219
 
220
        set_fr_iimmed   0xfffe,0xfffe,fr10
221
        set_fr_iimmed   0x0001,0x0002,fr11
222
        cmaddhus        fr10,fr11,fr12,cc4,0
223
        test_fr_limmed  0xdead,0xbeef,fr12
224
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
225
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
226
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
227
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
228
 
229
        set_spr_immed   0,msr0
230
        set_fr_iimmed   0x0002,0x0001,fr10
231
        set_fr_iimmed   0xfffe,0xfffe,fr11
232
        cmaddhus        fr10,fr11,fr12,cc4,0
233
        test_fr_limmed  0xdead,0xbeef,fr12
234
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
235
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
236
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
237
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
238
 
239
        set_fr_iimmed   0xbeef,0xdead,fr13
240
        set_spr_immed   0,msr0
241
        set_spr_immed   0,msr1
242
        set_fr_iimmed   0x0001,0x0001,fr10
243
        set_fr_iimmed   0x8000,0x8000,fr11
244
        cmaddhus.p      fr10,fr10,fr12,cc4,0
245
        cmaddhus        fr11,fr11,fr13,cc4,0
246
        test_fr_limmed  0xdead,0xbeef,fr12
247
        test_fr_limmed  0xbeef,0xdead,fr13
248
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
249
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
250
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
251
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
252
 
253
        set_fr_iimmed   0xdead,0xbeef,fr12
254
        set_spr_immed   0,msr0
255
        set_spr_immed   0,msr1
256
        set_fr_iimmed   0x0000,0x0000,fr10
257
        set_fr_iimmed   0x0000,0x0000,fr11
258
        cmaddhus        fr10,fr11,fr12,cc1,1
259
        test_fr_limmed  0xdead,0xbeef,fr12
260
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
261
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
262
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
263
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
264
 
265
        set_fr_iimmed   0xbeef,0x0000,fr10
266
        set_fr_iimmed   0x0000,0xdead,fr11
267
        cmaddhus        fr10,fr11,fr12,cc1,1
268
        test_fr_limmed  0xdead,0xbeef,fr12
269
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
270
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
271
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
272
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
273
 
274
        set_fr_iimmed   0x0000,0xdead,fr10
275
        set_fr_iimmed   0xbeef,0x0000,fr11
276
        cmaddhus        fr10,fr11,fr12,cc1,1
277
        test_fr_limmed  0xdead,0xbeef,fr12
278
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
279
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
280
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
281
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
282
 
283
        set_fr_iimmed   0x1234,0x5678,fr10
284
        set_fr_iimmed   0x1111,0x1111,fr11
285
        cmaddhus        fr10,fr11,fr12,cc1,1
286
        test_fr_limmed  0xdead,0xbeef,fr12
287
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
288
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
289
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
290
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
291
 
292
        set_fr_iimmed   0x7ffe,0x7ffe,fr10
293
        set_fr_iimmed   0x0002,0x0001,fr11
294
        cmaddhus        fr10,fr11,fr12,cc5,1
295
        test_fr_limmed  0xdead,0xbeef,fr12
296
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
297
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
298
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
299
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
300
 
301
        set_fr_iimmed   0xfffe,0xfffe,fr10
302
        set_fr_iimmed   0x0001,0x0002,fr11
303
        cmaddhus        fr10,fr11,fr12,cc5,1
304
        test_fr_limmed  0xdead,0xbeef,fr12
305
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
306
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
307
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
308
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
309
 
310
        set_spr_immed   0,msr0
311
        set_fr_iimmed   0x0002,0x0001,fr10
312
        set_fr_iimmed   0xfffe,0xfffe,fr11
313
        cmaddhus        fr10,fr11,fr12,cc5,1
314
        test_fr_limmed  0xdead,0xbeef,fr12
315
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
316
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
317
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
318
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
319
 
320
        set_fr_iimmed   0xbeef,0xdead,fr13
321
        set_spr_immed   0,msr0
322
        set_spr_immed   0,msr1
323
        set_fr_iimmed   0x0001,0x0001,fr10
324
        set_fr_iimmed   0x8000,0x8000,fr11
325
        cmaddhus.p      fr10,fr10,fr12,cc5,1
326
        cmaddhus        fr11,fr11,fr13,cc5,1
327
        test_fr_limmed  0xdead,0xbeef,fr12
328
        test_fr_limmed  0xbeef,0xdead,fr13
329
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
330
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
331
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
332
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
333
 
334
        set_fr_iimmed   0xdead,0xbeef,fr12
335
        set_spr_immed   0,msr0
336
        set_spr_immed   0,msr1
337
        set_fr_iimmed   0x0000,0x0000,fr10
338
        set_fr_iimmed   0x0000,0x0000,fr11
339
        cmaddhus        fr10,fr11,fr12,cc2,1
340
        test_fr_limmed  0xdead,0xbeef,fr12
341
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
342
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
343
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
344
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
345
 
346
        set_fr_iimmed   0xbeef,0x0000,fr10
347
        set_fr_iimmed   0x0000,0xdead,fr11
348
        cmaddhus        fr10,fr11,fr12,cc2,0
349
        test_fr_limmed  0xdead,0xbeef,fr12
350
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
351
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
352
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
353
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
354
 
355
        set_fr_iimmed   0x0000,0xdead,fr10
356
        set_fr_iimmed   0xbeef,0x0000,fr11
357
        cmaddhus        fr10,fr11,fr12,cc2,1
358
        test_fr_limmed  0xdead,0xbeef,fr12
359
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
360
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
361
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
362
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
363
 
364
        set_fr_iimmed   0x1234,0x5678,fr10
365
        set_fr_iimmed   0x1111,0x1111,fr11
366
        cmaddhus        fr10,fr11,fr12,cc2,0
367
        test_fr_limmed  0xdead,0xbeef,fr12
368
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
369
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
370
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
371
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
372
 
373
        set_fr_iimmed   0x7ffe,0x7ffe,fr10
374
        set_fr_iimmed   0x0002,0x0001,fr11
375
        cmaddhus        fr10,fr11,fr12,cc6,1
376
        test_fr_limmed  0xdead,0xbeef,fr12
377
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
378
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
379
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
380
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
381
 
382
        set_fr_iimmed   0xfffe,0xfffe,fr10
383
        set_fr_iimmed   0x0001,0x0002,fr11
384
        cmaddhus        fr10,fr11,fr12,cc6,0
385
        test_fr_limmed  0xdead,0xbeef,fr12
386
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
387
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
388
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
389
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
390
 
391
        set_spr_immed   0,msr0
392
        set_fr_iimmed   0x0002,0x0001,fr10
393
        set_fr_iimmed   0xfffe,0xfffe,fr11
394
        cmaddhus        fr10,fr11,fr12,cc6,1
395
        test_fr_limmed  0xdead,0xbeef,fr12
396
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
397
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
398
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
399
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
400
 
401
        set_fr_iimmed   0xbeef,0xdead,fr13
402
        set_spr_immed   0,msr0
403
        set_spr_immed   0,msr1
404
        set_fr_iimmed   0x0001,0x0001,fr10
405
        set_fr_iimmed   0x8000,0x8000,fr11
406
        cmaddhus.p      fr10,fr10,fr12,cc6,0
407
        cmaddhus        fr11,fr11,fr13,cc6,1
408
        test_fr_limmed  0xdead,0xbeef,fr12
409
        test_fr_limmed  0xbeef,0xdead,fr13
410
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
411
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
412
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
413
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
414
 
415
        set_fr_iimmed   0xdead,0xbeef,fr12
416
        set_spr_immed   0,msr0
417
        set_spr_immed   0,msr1
418
        set_fr_iimmed   0x0000,0x0000,fr10
419
        set_fr_iimmed   0x0000,0x0000,fr11
420
        cmaddhus        fr10,fr11,fr12,cc3,1
421
        test_fr_limmed  0xdead,0xbeef,fr12
422
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
423
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
424
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
425
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
426
 
427
        set_fr_iimmed   0xbeef,0x0000,fr10
428
        set_fr_iimmed   0x0000,0xdead,fr11
429
        cmaddhus        fr10,fr11,fr12,cc3,0
430
        test_fr_limmed  0xdead,0xbeef,fr12
431
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
432
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
433
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
434
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
435
 
436
        set_fr_iimmed   0x0000,0xdead,fr10
437
        set_fr_iimmed   0xbeef,0x0000,fr11
438
        cmaddhus        fr10,fr11,fr12,cc3,1
439
        test_fr_limmed  0xdead,0xbeef,fr12
440
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
441
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
442
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
443
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
444
 
445
        set_fr_iimmed   0x1234,0x5678,fr10
446
        set_fr_iimmed   0x1111,0x1111,fr11
447
        cmaddhus        fr10,fr11,fr12,cc3,0
448
        test_fr_limmed  0xdead,0xbeef,fr12
449
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
450
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
451
        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
452
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
453
 
454
        set_fr_iimmed   0x7ffe,0x7ffe,fr10
455
        set_fr_iimmed   0x0002,0x0001,fr11
456
        cmaddhus        fr10,fr11,fr12,cc7,1
457
        test_fr_limmed  0xdead,0xbeef,fr12
458
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
459
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
460
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
461
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
462
 
463
        set_fr_iimmed   0xfffe,0xfffe,fr10
464
        set_fr_iimmed   0x0001,0x0002,fr11
465
        cmaddhus        fr10,fr11,fr12,cc7,0
466
        test_fr_limmed  0xdead,0xbeef,fr12
467
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
468
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
469
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
470
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
471
 
472
        set_spr_immed   0,msr0
473
        set_fr_iimmed   0x0002,0x0001,fr10
474
        set_fr_iimmed   0xfffe,0xfffe,fr11
475
        cmaddhus        fr10,fr11,fr12,cc7,1
476
        test_fr_limmed  0xdead,0xbeef,fr12
477
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
478
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
479
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
480
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
481
 
482
        set_fr_iimmed   0xbeef,0xdead,fr13
483
        set_spr_immed   0,msr0
484
        set_spr_immed   0,msr1
485
        set_fr_iimmed   0x0001,0x0001,fr10
486
        set_fr_iimmed   0x8000,0x8000,fr11
487
        cmaddhus.p      fr10,fr10,fr12,cc7,0
488
        cmaddhus        fr11,fr11,fr13,cc7,1
489
        test_fr_limmed  0xdead,0xbeef,fr12
490
        test_fr_limmed  0xbeef,0xdead,fr13
491
        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
492
        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
493
        test_spr_bits   1,0,0,msr0              ; msr0.aovf set
494
        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
495
 
496
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.