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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [csrl.cgs] - Blame information for rev 157

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Line No. Rev Author Line
1 24 jeremybenn
# frv testcase for csrl $GRi,$GRj,$GRk,$CCi,$cond
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# mach: all
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        .include "testutils.inc"
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        start
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        .global csrl
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csrl:
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        set_spr_immed   0x1b1b,cccr
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        set_gr_limmed   0xdead,0xbee0,gr7       ; Shift by 0
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x05,0          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc0,1
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        test_icc        0 1 0 1 icc0
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbee1,gr7       ; Shift by 1
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,0          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc0,1
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        test_icc        1 1 1 1 icc0
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        test_gr_limmed  0x4000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; Shift by 31
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,0          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc4,1
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        test_icc        1 1 1 1 icc0
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        test_gr_immed   1,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; clear register
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        set_gr_limmed   0x4000,0x0000,gr8
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        set_icc         0x0a,0          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc4,1
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        test_icc        1 0 1 0 icc0
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        test_gr_immed   0x00000000,gr8
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        set_gr_limmed   0xdead,0xbee0,gr7       ; Shift by 0
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x05,0          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc0,0
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        test_icc        0 1 0 1 icc0
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbee1,gr7       ; Shift by 1
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,0          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc0,0
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        test_icc        1 1 1 1 icc0
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; Shift by 31
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,0          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc4,0
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        test_icc        1 1 1 1 icc0
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; clear register
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        set_gr_limmed   0x4000,0x0000,gr8
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        set_icc         0x0a,0          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc4,0
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        test_icc        1 0 1 0 icc0
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        test_gr_limmed  0x4000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbee0,gr7       ; Shift by 0
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x05,1          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc1,0
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        test_icc        0 1 0 1 icc1
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbee1,gr7       ; Shift by 1
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,1          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc1,0
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        test_icc        1 1 1 1 icc1
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        test_gr_limmed  0x4000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; Shift by 31
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,1          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc5,0
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        test_icc        1 1 1 1 icc1
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        test_gr_immed   1,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; clear register
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        set_gr_limmed   0x4000,0x0000,gr8
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        set_icc         0x0a,1          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc5,0
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        test_icc        1 0 1 0 icc1
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        test_gr_immed   0x00000000,gr8
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        set_gr_limmed   0xdead,0xbee0,gr7       ; Shift by 0
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x05,1          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc1,1
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        test_icc        0 1 0 1 icc1
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbee1,gr7       ; Shift by 1
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,1          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc1,1
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        test_icc        1 1 1 1 icc1
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; Shift by 31
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,1          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc5,1
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        test_icc        1 1 1 1 icc1
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; clear register
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        set_gr_limmed   0x4000,0x0000,gr8
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        set_icc         0x0a,1          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc5,1
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        test_icc        1 0 1 0 icc1
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        test_gr_limmed  0x4000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbee0,gr7       ; Shift by 0
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x05,2          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc2,0
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        test_icc        0 1 0 1 icc2
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbee1,gr7       ; Shift by 1
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,2          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc2,0
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        test_icc        1 1 1 1 icc2
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; Shift by 31
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,2          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc6,1
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        test_icc        1 1 1 1 icc2
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; clear register
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        set_gr_limmed   0x4000,0x0000,gr8
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        set_icc         0x0a,2          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc6,1
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        test_icc        1 0 1 0 icc2
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        test_gr_limmed  0x4000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbee0,gr7       ; Shift by 0
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x05,3          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc3,0
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        test_icc        0 1 0 1 icc3
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbee1,gr7       ; Shift by 1
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,3          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc3,0
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        test_icc        1 1 1 1 icc3
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; Shift by 31
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        set_gr_limmed   0x8000,0x0000,gr8
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        set_icc         0x0f,3          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc7,1
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        test_icc        1 1 1 1 icc3
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        test_gr_limmed  0x8000,0x0000,gr8
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        set_gr_limmed   0xdead,0xbeff,gr7       ; clear register
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        set_gr_limmed   0x4000,0x0000,gr8
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        set_icc         0x0a,3          ; Set mask opposite of expected
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        csrl            gr8,gr7,gr8,cc7,1
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        test_icc        1 0 1 0 icc3
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        test_gr_limmed  0x4000,0x0000,gr8
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        pass

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