OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [dcf.cgs] - Blame information for rev 407

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# FRV testcase for dcf @(GRi,GRj)
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global dcf
9
dcf:
10
        and_spr_immed   0x7fffffff,hsr0 ; data cache only: copy-back mode
11
        set_gr_addr     doit,gr10
12
        set_gr_immed    0,gr11
13
        set_gr_immed    1,gr12
14
        set_gr_immed    2,gr13
15
 
16
        set_spr_addr    ok1,lr
17
        bra             doit
18
ok1:    test_gr_immed   1,gr11
19
 
20
        set_mem_immed   0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache
21
        set_spr_addr    ok2,lr
22
        bra             doit
23
ok2:    test_gr_immed   2,gr11          ; still only added 1
24
 
25
        set_gr_addr     doit1,gr10
26
        set_mem_immed   0x9600b00d,gr10 ; change to add gr11,gr13,gr11 in cache
27
        dcf             @(gr10,gr0)     ; flush data cache
28
        set_spr_addr    ok3,lr
29
        bra             doit1
30
ok3:    test_gr_immed   4,gr11          ; added 2 this time
31
 
32
        pass
33
 
34
doit:   add             gr11,gr12,gr11
35
        bralr
36
 
37
doit1:  add             gr11,gr12,gr11
38
        bralr
39
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.