OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fbulr.cgs] - Blame information for rev 272

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# frv testcase for fbulr $FCCi,$hint
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global fbulr
9
fbulr:
10
        set_spr_addr    bad,lr
11
        set_fcc         0x0 0
12
        fbulr           fcc0,0
13
 
14
        set_spr_addr    ok2,lr
15
        set_fcc         0x1 1
16
        fbulr           fcc1,1
17
        fail
18
ok2:
19
        set_spr_addr    bad,lr
20
        set_fcc         0x2 2
21
        fbulr           fcc2,2
22
 
23
        set_spr_addr    ok4,lr
24
        set_fcc         0x3 3
25
        fbulr           fcc3,3
26
        fail
27
ok4:
28
        set_spr_addr    bad,lr
29
        set_fcc         0x4 0
30
        fbulr           fcc0,0
31
 
32
        set_spr_addr    ok6,lr
33
        set_fcc         0x5 1
34
        fbulr           fcc1,1
35
        fail
36
ok6:
37
        set_spr_addr    bad,lr
38
        set_fcc         0x6 2
39
        fbulr           fcc2,2
40
 
41
        set_spr_addr    ok8,lr
42
        set_fcc         0x7 3
43
        fbulr           fcc3,3
44
        fail
45
ok8:
46
        set_spr_addr    bad,lr
47
        set_fcc         0x8 0
48
        fbulr           fcc0,0
49
 
50
        set_spr_addr    oka,lr
51
        set_fcc         0x9 1
52
        fbulr           fcc1,1
53
        fail
54
oka:
55
        set_spr_addr    bad,lr
56
        set_fcc         0xa 2
57
        fbulr           fcc2,2
58
 
59
        set_spr_addr    okc,lr
60
        set_fcc         0xb 3
61
        fbulr           fcc3,3
62
        fail
63
okc:
64
        set_spr_addr    bad,lr
65
        set_fcc         0xc 0
66
        fbulr           fcc0,0
67
 
68
        set_spr_addr    oke,lr
69
        set_fcc         0xd 1
70
        fbulr           fcc1,1
71
        fail
72
oke:
73
        set_spr_addr    bad,lr
74
        set_fcc         0xe 2
75
        fbulr           fcc2,2
76
 
77
        set_spr_addr    okg,lr
78
        set_fcc         0xf 3
79
        fbulr           fcc3,3
80
        fail
81
okg:
82
        pass
83
bad:
84
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.