OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [fcbnolr.cgs] - Blame information for rev 157

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
# frv testcase for fcbnolr
2 
# mach: all
3 
 
4 
        .include "testutils.inc"
5 
 
6 
        start
7 
 
8 
        .global fcbnolr
9 
fcbnolr:
10 
        ; ccond is true
11 
        set_spr_immed   128,lcr
12 
        set_spr_addr    bad,lr
13 
 
14 
        set_fcc         0x0 0
15 
        fcbnolr
16 
        set_fcc         0x1 1
17 
        fcbnolr
18 
        set_fcc         0x2 2
19 
        fcbnolr
20 
        set_fcc         0x3 3
21 
        fcbnolr
22 
        set_fcc         0x4 0
23 
        fcbnolr
24 
        set_fcc         0x5 1
25 
        fcbnolr
26 
        set_fcc         0x6 2
27 
        fcbnolr
28 
        set_fcc         0x7 3
29 
        fcbnolr
30 
        set_fcc         0x8 0
31 
        fcbnolr
32 
        set_fcc         0x9 1
33 
        fcbnolr
34 
        set_fcc         0xa 2
35 
        fcbnolr
36 
        set_fcc         0xb 3
37 
        fcbnolr
38 
        set_fcc         0xc 0
39 
        fcbnolr
40 
        set_fcc         0xd 1
41 
        fcbnolr
42 
        set_fcc         0xe 2
43 
        fcbnolr
44 
        set_fcc         0xf 3
45 
        fcbnolr
46 
 
47 
        ; ccond is true
48 
        set_spr_immed   1,lcr
49 
        set_fcc         0x0 0
50 
        fcbnolr
51 
        set_spr_immed   1,lcr
52 
        set_fcc         0x1 1
53 
        fcbnolr
54 
        set_spr_immed   1,lcr
55 
        set_fcc         0x2 2
56 
        fcbnolr
57 
        set_spr_immed   1,lcr
58 
        set_fcc         0x3 3
59 
        fcbnolr
60 
        set_spr_immed   1,lcr
61 
        set_fcc         0x4 0
62 
        fcbnolr
63 
        set_spr_immed   1,lcr
64 
        set_fcc         0x5 1
65 
        fcbnolr
66 
        set_spr_immed   1,lcr
67 
        set_fcc         0x6 2
68 
        fcbnolr
69 
        set_spr_immed   1,lcr
70 
        set_fcc         0x7 3
71 
        fcbnolr
72 
        set_spr_immed   1,lcr
73 
        set_fcc         0x8 0
74 
        fcbnolr
75 
        set_spr_immed   1,lcr
76 
        set_fcc         0x9 1
77 
        fcbnolr
78 
        set_spr_immed   1,lcr
79 
        set_fcc         0xa 2
80 
        fcbnolr
81 
        set_spr_immed   1,lcr
82 
        set_fcc         0xb 3
83 
        fcbnolr
84 
        set_spr_immed   1,lcr
85 
        set_fcc         0xc 0
86 
        fcbnolr
87 
        set_spr_immed   1,lcr
88 
        set_fcc         0xd 1
89 
        fcbnolr
90 
        set_spr_immed   1,lcr
91 
        set_fcc         0xe 2
92 
        fcbnolr
93 
        set_spr_immed   1,lcr
94 
        set_fcc         0xf 3
95 
        fcbnolr
96 
 
97 
        ; ccond is false
98 
        set_spr_immed   128,lcr
99 
 
100 
        set_fcc         0x0 0
101 
        fcbnolr
102 
        set_fcc         0x1 1
103 
        fcbnolr
104 
        set_fcc         0x2 2
105 
        fcbnolr
106 
        set_fcc         0x3 3
107 
        fcbnolr
108 
        set_fcc         0x4 0
109 
        fcbnolr
110 
        set_fcc         0x5 1
111 
        fcbnolr
112 
        set_fcc         0x6 2
113 
        fcbnolr
114 
        set_fcc         0x7 3
115 
        fcbnolr
116 
        set_fcc         0x8 0
117 
        fcbnolr
118 
        set_fcc         0x9 1
119 
        fcbnolr
120 
        set_fcc         0xa 2
121 
        fcbnolr
122 
        set_fcc         0xb 3
123 
        fcbnolr
124 
        set_fcc         0xc 0
125 
        fcbnolr
126 
        set_fcc         0xd 1
127 
        fcbnolr
128 
        set_fcc         0xe 2
129 
        fcbnolr
130 
        set_fcc         0xf 3
131 
        fcbnolr
132 
 
133 
        ; ccond is false
134 
        set_spr_immed   1,lcr
135 
        set_fcc         0x0 0
136 
        fcbnolr
137 
        set_spr_immed   1,lcr
138 
        set_fcc         0x1 1
139 
        fcbnolr
140 
        set_spr_immed   1,lcr
141 
        set_fcc         0x2 2
142 
        fcbnolr
143 
        set_spr_immed   1,lcr
144 
        set_fcc         0x3 3
145 
        fcbnolr
146 
        set_spr_immed   1,lcr
147 
        set_fcc         0x4 0
148 
        fcbnolr
149 
        set_spr_immed   1,lcr
150 
        set_fcc         0x5 1
151 
        fcbnolr
152 
        set_spr_immed   1,lcr
153 
        set_fcc         0x6 2
154 
        fcbnolr
155 
        set_spr_immed   1,lcr
156 
        set_fcc         0x7 3
157 
        fcbnolr
158 
        set_spr_immed   1,lcr
159 
        set_fcc         0x8 0
160 
        fcbnolr
161 
        set_spr_immed   1,lcr
162 
        set_fcc         0x9 1
163 
        fcbnolr
164 
        set_spr_immed   1,lcr
165 
        set_fcc         0xa 2
166 
        fcbnolr
167 
        set_spr_immed   1,lcr
168 
        set_fcc         0xb 3
169 
        fcbnolr
170 
        set_spr_immed   1,lcr
171 
        set_fcc         0xc 0
172 
        fcbnolr
173 
        set_spr_immed   1,lcr
174 
        set_fcc         0xd 1
175 
        fcbnolr
176 
        set_spr_immed   1,lcr
177 
        set_fcc         0xe 2
178 
        fcbnolr
179 
        set_spr_immed   1,lcr
180 
        set_fcc         0xf 3
181 
        fcbnolr
182 
 
183 
        pass
184 
bad:
185 
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.