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jeremybenn |
# frv testcase for fcmps $GRi,$GRj,$FCCi_2
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# mach: fr500 fr550 frv
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.include "testutils.inc"
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float_constants
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start
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load_float_constants
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.global fcmps
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fcmps:
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set_fcc 0x7,0 ; Set mask opposite of expected
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fcmps fr0,fr0,fcc0
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test_fcc 0x8,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr4,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr8,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr12,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr16,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr20,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr24,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr28,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr32,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr36,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr40,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr44,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr48,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr0,fr52,fcc0
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test_fcc 0x4,0
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set_fcc 0xe,0 ; Set mask opposite of expected
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fcmps fr0,fr56,fcc0
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test_fcc 0x1,0
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set_fcc 0xe,0 ; Set mask opposite of expected
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fcmps fr0,fr60,fcc0
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test_fcc 0x1,0
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set_fcc 0xd,0 ; Set mask opposite of expected
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fcmps fr4,fr0,fcc0
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test_fcc 0x2,0
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set_fcc 0x7,0 ; Set mask opposite of expected
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fcmps fr4,fr4,fcc0
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test_fcc 0x8,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr8,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr12,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr16,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr20,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr24,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr28,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr32,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr36,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr40,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr44,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr48,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr4,fr52,fcc0
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test_fcc 0x4,0
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set_fcc 0xe,0 ; Set mask opposite of expected
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fcmps fr4,fr56,fcc0
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test_fcc 0x1,0
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set_fcc 0xe,0 ; Set mask opposite of expected
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fcmps fr4,fr60,fcc0
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test_fcc 0x1,0
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set_fcc 0xd,0 ; Set mask opposite of expected
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fcmps fr8,fr0,fcc0
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test_fcc 0x2,0
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set_fcc 0xd,0 ; Set mask opposite of expected
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fcmps fr8,fr4,fcc0
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test_fcc 0x2,0
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set_fcc 0x7,0 ; Set mask opposite of expected
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fcmps fr8,fr8,fcc0
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test_fcc 0x8,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr12,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr16,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr20,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr24,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr28,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr32,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr36,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr40,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr44,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr48,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr8,fr52,fcc0
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test_fcc 0x4,0
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set_fcc 0xe,0 ; Set mask opposite of expected
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fcmps fr8,fr56,fcc0
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test_fcc 0x1,0
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set_fcc 0xe,0 ; Set mask opposite of expected
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fcmps fr8,fr60,fcc0
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test_fcc 0x1,0
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set_fcc 0xd,0 ; Set mask opposite of expected
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fcmps fr12,fr0,fcc0
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test_fcc 0x2,0
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set_fcc 0xd,0 ; Set mask opposite of expected
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fcmps fr12,fr4,fcc0
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test_fcc 0x2,0
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set_fcc 0xd,0 ; Set mask opposite of expected
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fcmps fr12,fr8,fcc0
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test_fcc 0x2,0
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set_fcc 0x7,0 ; Set mask opposite of expected
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fcmps fr12,fr12,fcc0
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test_fcc 0x8,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr12,fr16,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr12,fr20,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr12,fr24,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr12,fr28,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr12,fr32,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr12,fr36,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr12,fr40,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr12,fr44,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr12,fr48,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr12,fr52,fcc0
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test_fcc 0x4,0
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set_fcc 0xe,0 ; Set mask opposite of expected
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fcmps fr12,fr56,fcc0
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test_fcc 0x1,0
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set_fcc 0xe,0 ; Set mask opposite of expected
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fcmps fr12,fr60,fcc0
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test_fcc 0x1,0
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set_fcc 0xd,0 ; Set mask opposite of expected
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fcmps fr16,fr0,fcc0
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test_fcc 0x2,0
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set_fcc 0xd,0 ; Set mask opposite of expected
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fcmps fr16,fr4,fcc0
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test_fcc 0x2,0
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set_fcc 0xd,0 ; Set mask opposite of expected
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fcmps fr16,fr8,fcc0
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test_fcc 0x2,0
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set_fcc 0xd,0 ; Set mask opposite of expected
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fcmps fr16,fr12,fcc0
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test_fcc 0x2,0
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set_fcc 0x7,0 ; Set mask opposite of expected
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fcmps fr16,fr16,fcc0
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test_fcc 0x8,0
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set_fcc 0x7,0 ; Set mask opposite of expected
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fcmps fr16,fr20,fcc0
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test_fcc 0x8,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr16,fr24,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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fcmps fr16,fr28,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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233 |
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fcmps fr16,fr32,fcc0
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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236 |
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fcmps fr16,fr36,fcc0
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237 |
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test_fcc 0x4,0
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set_fcc 0xb,0 ; Set mask opposite of expected
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239 |
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fcmps fr16,fr40,fcc0
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240 |
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test_fcc 0x4,0
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241 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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242 |
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fcmps fr16,fr44,fcc0
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243 |
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test_fcc 0x4,0
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244 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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245 |
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fcmps fr16,fr48,fcc0
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246 |
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test_fcc 0x4,0
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247 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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248 |
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fcmps fr16,fr52,fcc0
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249 |
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test_fcc 0x4,0
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250 |
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set_fcc 0xe,0 ; Set mask opposite of expected
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251 |
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fcmps fr16,fr56,fcc0
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252 |
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test_fcc 0x1,0
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253 |
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set_fcc 0xe,0 ; Set mask opposite of expected
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254 |
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fcmps fr16,fr60,fcc0
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255 |
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test_fcc 0x1,0
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256 |
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set_fcc 0xd,0 ; Set mask opposite of expected
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258 |
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fcmps fr20,fr0,fcc0
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259 |
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test_fcc 0x2,0
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260 |
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set_fcc 0xd,0 ; Set mask opposite of expected
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261 |
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fcmps fr20,fr4,fcc0
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262 |
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test_fcc 0x2,0
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263 |
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set_fcc 0xd,0 ; Set mask opposite of expected
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264 |
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fcmps fr20,fr8,fcc0
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265 |
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test_fcc 0x2,0
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266 |
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set_fcc 0xd,0 ; Set mask opposite of expected
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267 |
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fcmps fr20,fr12,fcc0
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268 |
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test_fcc 0x2,0
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269 |
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set_fcc 0x7,0 ; Set mask opposite of expected
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270 |
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fcmps fr20,fr16,fcc0
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271 |
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test_fcc 0x8,0
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272 |
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set_fcc 0x7,0 ; Set mask opposite of expected
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273 |
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fcmps fr20,fr20,fcc0
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274 |
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test_fcc 0x8,0
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275 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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276 |
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fcmps fr20,fr24,fcc0
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277 |
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test_fcc 0x4,0
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278 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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279 |
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fcmps fr20,fr28,fcc0
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280 |
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test_fcc 0x4,0
|
281 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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282 |
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fcmps fr20,fr32,fcc0
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283 |
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test_fcc 0x4,0
|
284 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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285 |
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fcmps fr20,fr36,fcc0
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286 |
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test_fcc 0x4,0
|
287 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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288 |
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fcmps fr20,fr40,fcc0
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289 |
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test_fcc 0x4,0
|
290 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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291 |
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fcmps fr20,fr44,fcc0
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292 |
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test_fcc 0x4,0
|
293 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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294 |
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fcmps fr20,fr48,fcc0
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295 |
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test_fcc 0x4,0
|
296 |
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set_fcc 0xb,0 ; Set mask opposite of expected
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297 |
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fcmps fr20,fr52,fcc0
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298 |
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test_fcc 0x4,0
|
299 |
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set_fcc 0xe,0 ; Set mask opposite of expected
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300 |
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fcmps fr20,fr56,fcc0
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301 |
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test_fcc 0x1,0
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302 |
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set_fcc 0xe,0 ; Set mask opposite of expected
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303 |
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fcmps fr20,fr60,fcc0
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304 |
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test_fcc 0x1,0
|
305 |
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306 |
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set_fcc 0xd,0 ; Set mask opposite of expected
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307 |
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fcmps fr24,fr0,fcc0
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308 |
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test_fcc 0x2,0
|
309 |
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set_fcc 0xd,0 ; Set mask opposite of expected
|
310 |
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fcmps fr24,fr4,fcc0
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311 |
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test_fcc 0x2,0
|
312 |
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set_fcc 0xd,0 ; Set mask opposite of expected
|
313 |
|
|
fcmps fr24,fr8,fcc0
|
314 |
|
|
test_fcc 0x2,0
|
315 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
316 |
|
|
fcmps fr24,fr12,fcc0
|
317 |
|
|
test_fcc 0x2,0
|
318 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
319 |
|
|
fcmps fr24,fr16,fcc0
|
320 |
|
|
test_fcc 0x2,0
|
321 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
322 |
|
|
fcmps fr24,fr20,fcc0
|
323 |
|
|
test_fcc 0x2,0
|
324 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
325 |
|
|
fcmps fr24,fr24,fcc0
|
326 |
|
|
test_fcc 0x8,0
|
327 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
328 |
|
|
fcmps fr24,fr28,fcc0
|
329 |
|
|
test_fcc 0x4,0
|
330 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
331 |
|
|
fcmps fr24,fr32,fcc0
|
332 |
|
|
test_fcc 0x4,0
|
333 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
334 |
|
|
fcmps fr24,fr36,fcc0
|
335 |
|
|
test_fcc 0x4,0
|
336 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
337 |
|
|
fcmps fr24,fr40,fcc0
|
338 |
|
|
test_fcc 0x4,0
|
339 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
340 |
|
|
fcmps fr24,fr44,fcc0
|
341 |
|
|
test_fcc 0x4,0
|
342 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
343 |
|
|
fcmps fr24,fr48,fcc0
|
344 |
|
|
test_fcc 0x4,0
|
345 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
346 |
|
|
fcmps fr24,fr52,fcc0
|
347 |
|
|
test_fcc 0x4,0
|
348 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
349 |
|
|
fcmps fr24,fr56,fcc0
|
350 |
|
|
test_fcc 0x1,0
|
351 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
352 |
|
|
fcmps fr24,fr60,fcc0
|
353 |
|
|
test_fcc 0x1,0
|
354 |
|
|
|
355 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
356 |
|
|
fcmps fr28,fr0,fcc0
|
357 |
|
|
test_fcc 0x2,0
|
358 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
359 |
|
|
fcmps fr28,fr4,fcc0
|
360 |
|
|
test_fcc 0x2,0
|
361 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
362 |
|
|
fcmps fr28,fr8,fcc0
|
363 |
|
|
test_fcc 0x2,0
|
364 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
365 |
|
|
fcmps fr28,fr12,fcc0
|
366 |
|
|
test_fcc 0x2,0
|
367 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
368 |
|
|
fcmps fr28,fr16,fcc0
|
369 |
|
|
test_fcc 0x2,0
|
370 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
371 |
|
|
fcmps fr28,fr20,fcc0
|
372 |
|
|
test_fcc 0x2,0
|
373 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
374 |
|
|
fcmps fr28,fr24,fcc0
|
375 |
|
|
test_fcc 0x2,0
|
376 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
377 |
|
|
fcmps fr28,fr28,fcc0
|
378 |
|
|
test_fcc 0x8,0
|
379 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
380 |
|
|
fcmps fr28,fr32,fcc0
|
381 |
|
|
test_fcc 0x4,0
|
382 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
383 |
|
|
fcmps fr28,fr36,fcc0
|
384 |
|
|
test_fcc 0x4,0
|
385 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
386 |
|
|
fcmps fr28,fr40,fcc0
|
387 |
|
|
test_fcc 0x4,0
|
388 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
389 |
|
|
fcmps fr28,fr44,fcc0
|
390 |
|
|
test_fcc 0x4,0
|
391 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
392 |
|
|
fcmps fr28,fr48,fcc0
|
393 |
|
|
test_fcc 0x4,0
|
394 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
395 |
|
|
fcmps fr28,fr52,fcc0
|
396 |
|
|
test_fcc 0x4,0
|
397 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
398 |
|
|
fcmps fr28,fr56,fcc0
|
399 |
|
|
test_fcc 0x1,0
|
400 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
401 |
|
|
fcmps fr28,fr60,fcc0
|
402 |
|
|
test_fcc 0x1,0
|
403 |
|
|
|
404 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
405 |
|
|
fcmps fr48,fr0,fcc0
|
406 |
|
|
test_fcc 0x2,0
|
407 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
408 |
|
|
fcmps fr48,fr4,fcc0
|
409 |
|
|
test_fcc 0x2,0
|
410 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
411 |
|
|
fcmps fr48,fr8,fcc0
|
412 |
|
|
test_fcc 0x2,0
|
413 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
414 |
|
|
fcmps fr48,fr12,fcc0
|
415 |
|
|
test_fcc 0x2,0
|
416 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
417 |
|
|
fcmps fr48,fr16,fcc0
|
418 |
|
|
test_fcc 0x2,0
|
419 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
420 |
|
|
fcmps fr48,fr20,fcc0
|
421 |
|
|
test_fcc 0x2,0
|
422 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
423 |
|
|
fcmps fr48,fr24,fcc0
|
424 |
|
|
test_fcc 0x2,0
|
425 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
426 |
|
|
fcmps fr48,fr28,fcc0
|
427 |
|
|
test_fcc 0x2,0
|
428 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
429 |
|
|
fcmps fr48,fr32,fcc0
|
430 |
|
|
test_fcc 0x2,0
|
431 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
432 |
|
|
fcmps fr48,fr36,fcc0
|
433 |
|
|
test_fcc 0x2,0
|
434 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
435 |
|
|
fcmps fr48,fr40,fcc0
|
436 |
|
|
test_fcc 0x2,0
|
437 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
438 |
|
|
fcmps fr48,fr44,fcc0
|
439 |
|
|
test_fcc 0x2,0
|
440 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
441 |
|
|
fcmps fr48,fr48,fcc0
|
442 |
|
|
test_fcc 0x8,0
|
443 |
|
|
set_fcc 0xb,0 ; Set mask opposite of expected
|
444 |
|
|
fcmps fr48,fr52,fcc0
|
445 |
|
|
test_fcc 0x4,0
|
446 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
447 |
|
|
fcmps fr48,fr56,fcc0
|
448 |
|
|
test_fcc 0x1,0
|
449 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
450 |
|
|
fcmps fr48,fr60,fcc0
|
451 |
|
|
test_fcc 0x1,0
|
452 |
|
|
|
453 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
454 |
|
|
fcmps fr52,fr0,fcc0
|
455 |
|
|
test_fcc 0x2,0
|
456 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
457 |
|
|
fcmps fr52,fr4,fcc0
|
458 |
|
|
test_fcc 0x2,0
|
459 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
460 |
|
|
fcmps fr52,fr8,fcc0
|
461 |
|
|
test_fcc 0x2,0
|
462 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
463 |
|
|
fcmps fr52,fr12,fcc0
|
464 |
|
|
test_fcc 0x2,0
|
465 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
466 |
|
|
fcmps fr52,fr16,fcc0
|
467 |
|
|
test_fcc 0x2,0
|
468 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
469 |
|
|
fcmps fr52,fr20,fcc0
|
470 |
|
|
test_fcc 0x2,0
|
471 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
472 |
|
|
fcmps fr52,fr24,fcc0
|
473 |
|
|
test_fcc 0x2,0
|
474 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
475 |
|
|
fcmps fr52,fr28,fcc0
|
476 |
|
|
test_fcc 0x2,0
|
477 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
478 |
|
|
fcmps fr52,fr32,fcc0
|
479 |
|
|
test_fcc 0x2,0
|
480 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
481 |
|
|
fcmps fr52,fr36,fcc0
|
482 |
|
|
test_fcc 0x2,0
|
483 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
484 |
|
|
fcmps fr52,fr40,fcc0
|
485 |
|
|
test_fcc 0x2,0
|
486 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
487 |
|
|
fcmps fr52,fr44,fcc0
|
488 |
|
|
test_fcc 0x2,0
|
489 |
|
|
set_fcc 0xd,0 ; Set mask opposite of expected
|
490 |
|
|
fcmps fr52,fr48,fcc0
|
491 |
|
|
test_fcc 0x2,0
|
492 |
|
|
set_fcc 0x7,0 ; Set mask opposite of expected
|
493 |
|
|
fcmps fr52,fr52,fcc0
|
494 |
|
|
test_fcc 0x8,0
|
495 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
496 |
|
|
fcmps fr52,fr56,fcc0
|
497 |
|
|
test_fcc 0x1,0
|
498 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
499 |
|
|
fcmps fr52,fr60,fcc0
|
500 |
|
|
test_fcc 0x1,0
|
501 |
|
|
|
502 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
503 |
|
|
fcmps fr56,fr0,fcc0
|
504 |
|
|
test_fcc 0x1,0
|
505 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
506 |
|
|
fcmps fr56,fr4,fcc0
|
507 |
|
|
test_fcc 0x1,0
|
508 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
509 |
|
|
fcmps fr56,fr8,fcc0
|
510 |
|
|
test_fcc 0x1,0
|
511 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
512 |
|
|
fcmps fr56,fr12,fcc0
|
513 |
|
|
test_fcc 0x1,0
|
514 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
515 |
|
|
fcmps fr56,fr16,fcc0
|
516 |
|
|
test_fcc 0x1,0
|
517 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
518 |
|
|
fcmps fr56,fr20,fcc0
|
519 |
|
|
test_fcc 0x1,0
|
520 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
521 |
|
|
fcmps fr56,fr24,fcc0
|
522 |
|
|
test_fcc 0x1,0
|
523 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
524 |
|
|
fcmps fr56,fr28,fcc0
|
525 |
|
|
test_fcc 0x1,0
|
526 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
527 |
|
|
fcmps fr56,fr32,fcc0
|
528 |
|
|
test_fcc 0x1,0
|
529 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
530 |
|
|
fcmps fr56,fr36,fcc0
|
531 |
|
|
test_fcc 0x1,0
|
532 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
533 |
|
|
fcmps fr56,fr40,fcc0
|
534 |
|
|
test_fcc 0x1,0
|
535 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
536 |
|
|
fcmps fr56,fr44,fcc0
|
537 |
|
|
test_fcc 0x1,0
|
538 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
539 |
|
|
fcmps fr56,fr48,fcc0
|
540 |
|
|
test_fcc 0x1,0
|
541 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
542 |
|
|
fcmps fr56,fr52,fcc0
|
543 |
|
|
test_fcc 0x1,0
|
544 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
545 |
|
|
fcmps fr56,fr56,fcc0
|
546 |
|
|
test_fcc 0x1,0
|
547 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
548 |
|
|
fcmps fr56,fr60,fcc0
|
549 |
|
|
test_fcc 0x1,0
|
550 |
|
|
|
551 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
552 |
|
|
fcmps fr60,fr0,fcc0
|
553 |
|
|
test_fcc 0x1,0
|
554 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
555 |
|
|
fcmps fr60,fr4,fcc0
|
556 |
|
|
test_fcc 0x1,0
|
557 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
558 |
|
|
fcmps fr60,fr8,fcc0
|
559 |
|
|
test_fcc 0x1,0
|
560 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
561 |
|
|
fcmps fr60,fr12,fcc0
|
562 |
|
|
test_fcc 0x1,0
|
563 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
564 |
|
|
fcmps fr60,fr16,fcc0
|
565 |
|
|
test_fcc 0x1,0
|
566 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
567 |
|
|
fcmps fr60,fr20,fcc0
|
568 |
|
|
test_fcc 0x1,0
|
569 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
570 |
|
|
fcmps fr60,fr24,fcc0
|
571 |
|
|
test_fcc 0x1,0
|
572 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
573 |
|
|
fcmps fr60,fr28,fcc0
|
574 |
|
|
test_fcc 0x1,0
|
575 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
576 |
|
|
fcmps fr60,fr32,fcc0
|
577 |
|
|
test_fcc 0x1,0
|
578 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
579 |
|
|
fcmps fr60,fr36,fcc0
|
580 |
|
|
test_fcc 0x1,0
|
581 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
582 |
|
|
fcmps fr60,fr40,fcc0
|
583 |
|
|
test_fcc 0x1,0
|
584 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
585 |
|
|
fcmps fr60,fr44,fcc0
|
586 |
|
|
test_fcc 0x1,0
|
587 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
588 |
|
|
fcmps fr60,fr48,fcc0
|
589 |
|
|
test_fcc 0x1,0
|
590 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
591 |
|
|
fcmps fr60,fr52,fcc0
|
592 |
|
|
test_fcc 0x1,0
|
593 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
594 |
|
|
fcmps fr60,fr56,fcc0
|
595 |
|
|
test_fcc 0x1,0
|
596 |
|
|
set_fcc 0xe,0 ; Set mask opposite of expected
|
597 |
|
|
fcmps fr60,fr60,fcc0
|
598 |
|
|
test_fcc 0x1,0
|
599 |
|
|
|
600 |
|
|
pass
|