OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [ftino.cgs] - Blame information for rev 157

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# frv testcase for ftino
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global ftinev
9
ftinev:
10
        and_spr_immed   -4081,tbr               ; clear tbr.tt
11
        set_gr_spr      tbr,gr7
12
        inc_gr_immed    2112,gr7                ; address of exception handler
13
        set_mem_limmed  0x0038,0x2000,gr7       ; bctrlr 0,0
14
 
15
        set_spr_immed   128,lcr
16
        set_spr_addr    bad,lr
17
        set_gr_immed    0,gr7
18
 
19
        set_fcc         0x0 0
20
        ftino                   ; should branch to tbr + (128 + 4)*16
21
        set_fcc         0x1 0
22
        ftino                   ; should branch to tbr + (128 + 4)*16
23
        set_fcc         0x2 0
24
        ftino                   ; should branch to tbr + (128 + 4)*16
25
        set_fcc         0x3 0
26
        ftino                   ; should branch to tbr + (128 + 4)*16
27
        set_fcc         0x4 0
28
        ftino                   ; should branch to tbr + (128 + 4)*16
29
        set_fcc         0x5 0
30
        ftino                   ; should branch to tbr + (128 + 4)*16
31
        set_fcc         0x6 0
32
        ftino                   ; should branch to tbr + (128 + 4)*16
33
        set_fcc         0x7 0
34
        ftino                   ; should branch to tbr + (128 + 4)*16
35
        set_fcc         0x8 0
36
        ftino                   ; should branch to tbr + (128 + 4)*16
37
        set_fcc         0x9 0
38
        ftino                   ; should branch to tbr + (128 + 4)*16
39
        set_fcc         0xa 0
40
        ftino                   ; should branch to tbr + (128 + 4)*16
41
        set_fcc         0xb 0
42
        ftino                   ; should branch to tbr + (128 + 4)*16
43
        set_fcc         0xc 0
44
        ftino                   ; should branch to tbr + (128 + 4)*16
45
        set_fcc         0xd 0
46
        ftino                   ; should branch to tbr + (128 + 4)*16
47
        set_fcc         0xe 0
48
        ftino                   ; should branch to tbr + (128 + 4)*16
49
        set_fcc         0xf 0
50
        ftino                   ; should branch to tbr + (128 + 4)*16
51
        pass
52
bad:
53
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.