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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [ftiuge.cgs] - Blame information for rev 407

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# frv testcase for ftiuge $FCCi_2,$GRi,$s12
# mach: all
 
        .include "testutils.inc"
 
        start
 
        .global ftiuge
ftiuge:
        and_spr_immed   -4081,tbr               ; clear tbr.tt
        set_gr_spr      tbr,gr7
        inc_gr_immed    2112,gr7                ; address of exception handler
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
 
        set_spr_immed   128,lcr
        set_gr_immed    0,gr7
 
        set_spr_addr    bad,lr
        set_fcc         0x0 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok1,lr
        set_fcc         0x1 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok1:
        set_psr_et      1
        set_spr_addr    ok2,lr
        set_fcc         0x2 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok2:
        set_psr_et      1
        set_spr_addr    ok3,lr
        set_fcc         0x3 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok3:
        set_spr_addr    bad,lr
        set_fcc         0x4 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
 
        set_psr_et      1
        set_spr_addr    ok5,lr
        set_fcc         0x5 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok5:
        set_psr_et      1
        set_spr_addr    ok6,lr
        set_fcc         0x6 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok6:
        set_psr_et      1
        set_spr_addr    ok7,lr
        set_fcc         0x7 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok7:
        set_psr_et      1
        set_spr_addr    ok8,lr
        set_fcc         0x8 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok8:
        set_psr_et      1
        set_spr_addr    ok9,lr
        set_fcc         0x9 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
ok9:
        set_psr_et      1
        set_spr_addr    oka,lr
        set_fcc         0xa 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
oka:
        set_psr_et      1
        set_spr_addr    okb,lr
        set_fcc         0xb 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okb:
        set_psr_et      1
        set_spr_addr    okc,lr
        set_fcc         0xc 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okc:
        set_psr_et      1
        set_spr_addr    okd,lr
        set_fcc         0xd 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okd:
        set_psr_et      1
        set_spr_addr    oke,lr
        set_fcc         0xe 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
oke:
        set_psr_et      1
        set_spr_addr    okf,lr
        set_fcc         0xf 0
        ftiuge          fcc0,gr7,4      ; should branch to tbr + (128 + 4)*16
        fail
okf:
        pass
bad:
        fail

Line No.	Rev	Author	Line
1	24	jeremybenn	`# frv testcase for ftiuge $FCCi_2,$GRi,$s12`
2			`# mach: all`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global ftiuge`
9			`ftiuge:`
10			`and_spr_immed -4081,tbr ; clear tbr.tt`
11			`set_gr_spr tbr,gr7`
12			`inc_gr_immed 2112,gr7 ; address of exception handler`
13			`set_bctrlr_0_0 gr7 ; bctrlr 0,0`
14
15			`set_spr_immed 128,lcr`
16			`set_gr_immed 0,gr7`
17
18			`set_spr_addr bad,lr`
19			`set_fcc 0x0 0`
20			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
21
22			`set_psr_et 1`
23			`set_spr_addr ok1,lr`
24			`set_fcc 0x1 0`
25			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
26			`fail`
27			`ok1:`
28			`set_psr_et 1`
29			`set_spr_addr ok2,lr`
30			`set_fcc 0x2 0`
31			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
32			`fail`
33			`ok2:`
34			`set_psr_et 1`
35			`set_spr_addr ok3,lr`
36			`set_fcc 0x3 0`
37			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
38			`fail`
39			`ok3:`
40			`set_spr_addr bad,lr`
41			`set_fcc 0x4 0`
42			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
43
44			`set_psr_et 1`
45			`set_spr_addr ok5,lr`
46			`set_fcc 0x5 0`
47			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
48			`fail`
49			`ok5:`
50			`set_psr_et 1`
51			`set_spr_addr ok6,lr`
52			`set_fcc 0x6 0`
53			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
54			`fail`
55			`ok6:`
56			`set_psr_et 1`
57			`set_spr_addr ok7,lr`
58			`set_fcc 0x7 0`
59			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
60			`fail`
61			`ok7:`
62			`set_psr_et 1`
63			`set_spr_addr ok8,lr`
64			`set_fcc 0x8 0`
65			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
66			`fail`
67			`ok8:`
68			`set_psr_et 1`
69			`set_spr_addr ok9,lr`
70			`set_fcc 0x9 0`
71			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
72			`fail`
73			`ok9:`
74			`set_psr_et 1`
75			`set_spr_addr oka,lr`
76			`set_fcc 0xa 0`
77			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
78			`fail`
79			`oka:`
80			`set_psr_et 1`
81			`set_spr_addr okb,lr`
82			`set_fcc 0xb 0`
83			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
84			`fail`
85			`okb:`
86			`set_psr_et 1`
87			`set_spr_addr okc,lr`
88			`set_fcc 0xc 0`
89			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
90			`fail`
91			`okc:`
92			`set_psr_et 1`
93			`set_spr_addr okd,lr`
94			`set_fcc 0xd 0`
95			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
96			`fail`
97			`okd:`
98			`set_psr_et 1`
99			`set_spr_addr oke,lr`
100			`set_fcc 0xe 0`
101			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
102			`fail`
103			`oke:`
104			`set_psr_et 1`
105			`set_spr_addr okf,lr`
106			`set_fcc 0xf 0`
107			`ftiuge fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16`
108			`fail`
109			`okf:`
110			`pass`
111			`bad:`
112			`fail`

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Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [ftiuge.cgs] - Blame information for rev 407