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# FRV testcase for handling of shadow registers SR0-SR4
# mach: frv
 
        .include "testutils.inc"
 
        start
 
        .global tra
tra:
        test_spr_bits   0x800,11,1,psr  ; PSR.ESR set
        test_spr_bits   0x4,2,1,psr     ; PSR.S set
 
        ; Set up exception handler for later
        and_spr_immed   -4081,tbr               ; clear tbr.tt
        set_gr_spr      tbr,gr7
        inc_gr_immed    2112,gr7                ; address of exception handler
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
        set_spr_immed   128,lcr
        set_psr_et      1
 
        set_gr_immed    0x11111111,gr4  ; SGR4-7
        set_gr_immed    0x22222222,gr5
        set_gr_immed    0x33333333,gr6
        set_gr_immed    0x44444444,gr7
        set_spr_immed   0x55555555,sr0  ; UGR4-7
        set_spr_immed   0x66666666,sr1
        set_spr_immed   0x77777777,sr2
        set_spr_immed   0x88888888,sr3
 
        and_spr_immed   0xfffff7ff,psr  ; turn off PSR.ESR
        test_gr_immed   0x11111111,gr4  ; SGR4-7
        test_gr_immed   0x22222222,gr5
        test_gr_immed   0x33333333,gr6
        test_gr_immed   0x44444444,gr7
        test_spr_immed  0x11111111,sr0  ; SGR4-7
        test_spr_immed  0x22222222,sr1
        test_spr_immed  0x33333333,sr2
        test_spr_immed  0x44444444,sr3
 
        set_spr_immed   0x55555555,sr0  ; SGR4-7
        set_spr_immed   0x66666666,sr1
        set_spr_immed   0x77777777,sr2
        set_spr_immed   0x88888888,sr3
        test_gr_immed   0x55555555,gr4  ; SGR4-7
        test_gr_immed   0x66666666,gr5
        test_gr_immed   0x77777777,gr6
        test_gr_immed   0x88888888,gr7
        test_spr_immed  0x55555555,sr0  ; SGR4-7
        test_spr_immed  0x66666666,sr1
        test_spr_immed  0x77777777,sr2
        test_spr_immed  0x88888888,sr3
 
        set_gr_immed    0x11111111,gr4  ; SGR4-7
        set_gr_immed    0x22222222,gr5
        set_gr_immed    0x33333333,gr6
        set_gr_immed    0x44444444,gr7
        test_gr_immed   0x11111111,gr4  ; SGR4-7
        test_gr_immed   0x22222222,gr5
        test_gr_immed   0x33333333,gr6
        test_gr_immed   0x44444444,gr7
        test_spr_immed  0x11111111,sr0  ; SGR4-7
        test_spr_immed  0x22222222,sr1
        test_spr_immed  0x33333333,sr2
        test_spr_immed  0x44444444,sr3
 
        or_spr_immed    0x00000800,psr  ; turn on PSR.ESR
        test_gr_immed   0x11111111,gr4  ; SGR4-7 -- SR0-3 (UGR4-7) are undefined
        test_gr_immed   0x22222222,gr5
        test_gr_immed   0x33333333,gr6
        test_gr_immed   0x44444444,gr7
 
        set_spr_immed   0x55555555,sr0  ; UGR4-7
        set_spr_immed   0x66666666,sr1
        set_spr_immed   0x77777777,sr2
        set_spr_immed   0x88888888,sr3
        test_gr_immed   0x11111111,gr4  ; SGR4-7
        test_gr_immed   0x22222222,gr5
        test_gr_immed   0x33333333,gr6
        test_gr_immed   0x44444444,gr7
        test_spr_immed  0x55555555,sr0  ; UGR4-7
        test_spr_immed  0x66666666,sr1
        test_spr_immed  0x77777777,sr2
        test_spr_immed  0x88888888,sr3
 
        and_spr_immed   0xfffffffb,psr  ; turn off PSR.S
        test_spr_immed  0x11111111,sr0  ; SGR4-7
        test_spr_immed  0x22222222,sr1
        test_spr_immed  0x33333333,sr2
        test_spr_immed  0x44444444,sr3
        test_gr_immed   0x55555555,gr4  ; UGR4-7
        test_gr_immed   0x66666666,gr5
        test_gr_immed   0x77777777,gr6
        test_gr_immed   0x88888888,gr7
 
        ; need to generate a trap to return to supervisor mode
        set_spr_addr    ok0,lr
        tira            gr0,4           ; should branch to tbr + (128 + 4)*16
 
        test_spr_bits   0x800,11,0,psr  ; PSR.ESR clear
        test_spr_bits   0x4,2,0,psr     ; PSR.S clear
        test_gr_immed   0x11111111,gr4  ; SGR4-7
        test_gr_immed   0x22222222,gr5
        test_gr_immed   0x33333333,gr6
        test_gr_immed   0x44444444,gr7
        test_spr_immed  0x11111111,sr0  ; SGR4-7
        test_spr_immed  0x22222222,sr1
        test_spr_immed  0x33333333,sr2
        test_spr_immed  0x44444444,sr3
 
        set_gr_immed    0x55555555,gr4  ; SGR4-7
        set_gr_immed    0x66666666,gr5
        set_gr_immed    0x77777777,gr6
        set_gr_immed    0x88888888,gr7
        test_gr_immed   0x55555555,gr4  ; SGR4-7
        test_gr_immed   0x66666666,gr5
        test_gr_immed   0x77777777,gr6
        test_gr_immed   0x88888888,gr7
        test_spr_immed  0x55555555,sr0  ; SGR4-7
        test_spr_immed  0x66666666,sr1
        test_spr_immed  0x77777777,sr2
        test_spr_immed  0x88888888,sr3
 
        set_gr_immed    0x11111111,gr4  ; SGR4-7
        set_gr_immed    0x22222222,gr5
        set_gr_immed    0x33333333,gr6
        set_gr_immed    0x44444444,gr7
        test_gr_immed   0x11111111,gr4  ; SGR4-7
        test_gr_immed   0x22222222,gr5
        test_gr_immed   0x33333333,gr6
        test_gr_immed   0x44444444,gr7
        test_spr_immed  0x11111111,sr0  ; SGR4-7
        test_spr_immed  0x22222222,sr1
        test_spr_immed  0x33333333,sr2
        test_spr_immed  0x44444444,sr3
 
        ; need to generate a trap to return to supervisor mode
        set_spr_addr    ok1,lr
        tira            gr0,4           ; should branch to tbr + (128 + 4)*16
 
        pass
 
ok0:    ; exception handler should branch here the first time
        test_spr_bits   0x800,11,1,psr  ; PSR.ESR set
        test_spr_bits   0x4,2,1,psr     ; PSR.S set
        test_gr_immed   0x11111111,gr4  ; SGR4-7
        test_gr_immed   0x22222222,gr5
        test_gr_immed   0x33333333,gr6
        test_gr_immed   0x44444444,gr7
        test_spr_immed  0x55555555,sr0  ; UGR4-7
        test_spr_immed  0x66666666,sr1
        test_spr_immed  0x77777777,sr2
        test_spr_immed  0x88888888,sr3
 
        and_spr_immed   0xfffff7ff,psr  ; turn off PSR.ESR
        test_gr_immed   0x11111111,gr4  ; SGR4-7
        test_gr_immed   0x22222222,gr5
        test_gr_immed   0x33333333,gr6
        test_gr_immed   0x44444444,gr7
        test_spr_immed  0x11111111,sr0  ; SGR4-7
        test_spr_immed  0x22222222,sr1
        test_spr_immed  0x33333333,sr2
        test_spr_immed  0x44444444,sr3
        rett            0
        fail
 
ok1:    ; exception handler should branch here the second time
        test_spr_bits   0x800,11,0,psr  ; PSR.ESR clear
        test_spr_bits   0x4,2,1,psr     ; PSR.S set
 
        test_gr_immed   0x11111111,gr4  ; SGR4-7
        test_gr_immed   0x22222222,gr5
        test_gr_immed   0x33333333,gr6
        test_gr_immed   0x44444444,gr7
        test_spr_immed  0x11111111,sr0  ; SGR4-7
        test_spr_immed  0x22222222,sr1
        test_spr_immed  0x33333333,sr2
        test_spr_immed  0x44444444,sr3
 
        set_spr_immed   0x55555555,sr0  ; SGR4-7
        set_spr_immed   0x66666666,sr1
        set_spr_immed   0x77777777,sr2
        set_spr_immed   0x88888888,sr3
        test_gr_immed   0x55555555,gr4  ; SGR4-7
        test_gr_immed   0x66666666,gr5
        test_gr_immed   0x77777777,gr6
        test_gr_immed   0x88888888,gr7
        test_spr_immed  0x55555555,sr0  ; SGR4-7
        test_spr_immed  0x66666666,sr1
        test_spr_immed  0x77777777,sr2
        test_spr_immed  0x88888888,sr3
 
        set_gr_immed    0x11111111,gr4  ; SGR4-7
        set_gr_immed    0x22222222,gr5
        set_gr_immed    0x33333333,gr6
        set_gr_immed    0x44444444,gr7
        test_gr_immed   0x11111111,gr4  ; SGR4-7
        test_gr_immed   0x22222222,gr5
        test_gr_immed   0x33333333,gr6
        test_gr_immed   0x44444444,gr7
        test_spr_immed  0x11111111,sr0  ; SGR4-7
        test_spr_immed  0x22222222,sr1
        test_spr_immed  0x33333333,sr2
        test_spr_immed  0x44444444,sr3
        rett            0
        fail

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [interrupts/] [shadow_regs.cgs] - Blame information for rev 157

Line No.	Rev	Author	Line
1	24	jeremybenn	`# FRV testcase for handling of shadow registers SR0-SR4`
2			`# mach: frv`
3
4			`.include "testutils.inc"`
5
6			`start`
7
8			`.global tra`
9			`tra:`
10			`test_spr_bits 0x800,11,1,psr ; PSR.ESR set`
11			`test_spr_bits 0x4,2,1,psr ; PSR.S set`
12
13			`; Set up exception handler for later`
14			`and_spr_immed -4081,tbr ; clear tbr.tt`
15			`set_gr_spr tbr,gr7`
16			`inc_gr_immed 2112,gr7 ; address of exception handler`
17			`set_bctrlr_0_0 gr7 ; bctrlr 0,0`
18			`set_spr_immed 128,lcr`
19			`set_psr_et 1`
20
21			`set_gr_immed 0x11111111,gr4 ; SGR4-7`
22			`set_gr_immed 0x22222222,gr5`
23			`set_gr_immed 0x33333333,gr6`
24			`set_gr_immed 0x44444444,gr7`
25			`set_spr_immed 0x55555555,sr0 ; UGR4-7`
26			`set_spr_immed 0x66666666,sr1`
27			`set_spr_immed 0x77777777,sr2`
28			`set_spr_immed 0x88888888,sr3`
29
30			`and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR`
31			`test_gr_immed 0x11111111,gr4 ; SGR4-7`
32			`test_gr_immed 0x22222222,gr5`
33			`test_gr_immed 0x33333333,gr6`
34			`test_gr_immed 0x44444444,gr7`
35			`test_spr_immed 0x11111111,sr0 ; SGR4-7`
36			`test_spr_immed 0x22222222,sr1`
37			`test_spr_immed 0x33333333,sr2`
38			`test_spr_immed 0x44444444,sr3`
39
40			`set_spr_immed 0x55555555,sr0 ; SGR4-7`
41			`set_spr_immed 0x66666666,sr1`
42			`set_spr_immed 0x77777777,sr2`
43			`set_spr_immed 0x88888888,sr3`
44			`test_gr_immed 0x55555555,gr4 ; SGR4-7`
45			`test_gr_immed 0x66666666,gr5`
46			`test_gr_immed 0x77777777,gr6`
47			`test_gr_immed 0x88888888,gr7`
48			`test_spr_immed 0x55555555,sr0 ; SGR4-7`
49			`test_spr_immed 0x66666666,sr1`
50			`test_spr_immed 0x77777777,sr2`
51			`test_spr_immed 0x88888888,sr3`
52
53			`set_gr_immed 0x11111111,gr4 ; SGR4-7`
54			`set_gr_immed 0x22222222,gr5`
55			`set_gr_immed 0x33333333,gr6`
56			`set_gr_immed 0x44444444,gr7`
57			`test_gr_immed 0x11111111,gr4 ; SGR4-7`
58			`test_gr_immed 0x22222222,gr5`
59			`test_gr_immed 0x33333333,gr6`
60			`test_gr_immed 0x44444444,gr7`
61			`test_spr_immed 0x11111111,sr0 ; SGR4-7`
62			`test_spr_immed 0x22222222,sr1`
63			`test_spr_immed 0x33333333,sr2`
64			`test_spr_immed 0x44444444,sr3`
65
66			`or_spr_immed 0x00000800,psr ; turn on PSR.ESR`
67			`test_gr_immed 0x11111111,gr4 ; SGR4-7 -- SR0-3 (UGR4-7) are undefined`
68			`test_gr_immed 0x22222222,gr5`
69			`test_gr_immed 0x33333333,gr6`
70			`test_gr_immed 0x44444444,gr7`
71
72			`set_spr_immed 0x55555555,sr0 ; UGR4-7`
73			`set_spr_immed 0x66666666,sr1`
74			`set_spr_immed 0x77777777,sr2`
75			`set_spr_immed 0x88888888,sr3`
76			`test_gr_immed 0x11111111,gr4 ; SGR4-7`
77			`test_gr_immed 0x22222222,gr5`
78			`test_gr_immed 0x33333333,gr6`
79			`test_gr_immed 0x44444444,gr7`
80			`test_spr_immed 0x55555555,sr0 ; UGR4-7`
81			`test_spr_immed 0x66666666,sr1`
82			`test_spr_immed 0x77777777,sr2`
83			`test_spr_immed 0x88888888,sr3`
84
85			`and_spr_immed 0xfffffffb,psr ; turn off PSR.S`
86			`test_spr_immed 0x11111111,sr0 ; SGR4-7`
87			`test_spr_immed 0x22222222,sr1`
88			`test_spr_immed 0x33333333,sr2`
89			`test_spr_immed 0x44444444,sr3`
90			`test_gr_immed 0x55555555,gr4 ; UGR4-7`
91			`test_gr_immed 0x66666666,gr5`
92			`test_gr_immed 0x77777777,gr6`
93			`test_gr_immed 0x88888888,gr7`
94
95			`; need to generate a trap to return to supervisor mode`
96			`set_spr_addr ok0,lr`
97			`tira gr0,4 ; should branch to tbr + (128 + 4)*16`
98
99			`test_spr_bits 0x800,11,0,psr ; PSR.ESR clear`
100			`test_spr_bits 0x4,2,0,psr ; PSR.S clear`
101			`test_gr_immed 0x11111111,gr4 ; SGR4-7`
102			`test_gr_immed 0x22222222,gr5`
103			`test_gr_immed 0x33333333,gr6`
104			`test_gr_immed 0x44444444,gr7`
105			`test_spr_immed 0x11111111,sr0 ; SGR4-7`
106			`test_spr_immed 0x22222222,sr1`
107			`test_spr_immed 0x33333333,sr2`
108			`test_spr_immed 0x44444444,sr3`
109
110			`set_gr_immed 0x55555555,gr4 ; SGR4-7`
111			`set_gr_immed 0x66666666,gr5`
112			`set_gr_immed 0x77777777,gr6`
113			`set_gr_immed 0x88888888,gr7`
114			`test_gr_immed 0x55555555,gr4 ; SGR4-7`
115			`test_gr_immed 0x66666666,gr5`
116			`test_gr_immed 0x77777777,gr6`
117			`test_gr_immed 0x88888888,gr7`
118			`test_spr_immed 0x55555555,sr0 ; SGR4-7`
119			`test_spr_immed 0x66666666,sr1`
120			`test_spr_immed 0x77777777,sr2`
121			`test_spr_immed 0x88888888,sr3`
122
123			`set_gr_immed 0x11111111,gr4 ; SGR4-7`
124			`set_gr_immed 0x22222222,gr5`
125			`set_gr_immed 0x33333333,gr6`
126			`set_gr_immed 0x44444444,gr7`
127			`test_gr_immed 0x11111111,gr4 ; SGR4-7`
128			`test_gr_immed 0x22222222,gr5`
129			`test_gr_immed 0x33333333,gr6`
130			`test_gr_immed 0x44444444,gr7`
131			`test_spr_immed 0x11111111,sr0 ; SGR4-7`
132			`test_spr_immed 0x22222222,sr1`
133			`test_spr_immed 0x33333333,sr2`
134			`test_spr_immed 0x44444444,sr3`
135
136			`; need to generate a trap to return to supervisor mode`
137			`set_spr_addr ok1,lr`
138			`tira gr0,4 ; should branch to tbr + (128 + 4)*16`
139
140			`pass`
141
142			`ok0: ; exception handler should branch here the first time`
143			`test_spr_bits 0x800,11,1,psr ; PSR.ESR set`
144			`test_spr_bits 0x4,2,1,psr ; PSR.S set`
145			`test_gr_immed 0x11111111,gr4 ; SGR4-7`
146			`test_gr_immed 0x22222222,gr5`
147			`test_gr_immed 0x33333333,gr6`
148			`test_gr_immed 0x44444444,gr7`
149			`test_spr_immed 0x55555555,sr0 ; UGR4-7`
150			`test_spr_immed 0x66666666,sr1`
151			`test_spr_immed 0x77777777,sr2`
152			`test_spr_immed 0x88888888,sr3`
153
154			`and_spr_immed 0xfffff7ff,psr ; turn off PSR.ESR`
155			`test_gr_immed 0x11111111,gr4 ; SGR4-7`
156			`test_gr_immed 0x22222222,gr5`
157			`test_gr_immed 0x33333333,gr6`
158			`test_gr_immed 0x44444444,gr7`
159			`test_spr_immed 0x11111111,sr0 ; SGR4-7`
160			`test_spr_immed 0x22222222,sr1`
161			`test_spr_immed 0x33333333,sr2`
162			`test_spr_immed 0x44444444,sr3`
163			`rett 0`
164			`fail`
165
166			`ok1: ; exception handler should branch here the second time`
167			`test_spr_bits 0x800,11,0,psr ; PSR.ESR clear`
168			`test_spr_bits 0x4,2,1,psr ; PSR.S set`
169
170			`test_gr_immed 0x11111111,gr4 ; SGR4-7`
171			`test_gr_immed 0x22222222,gr5`
172			`test_gr_immed 0x33333333,gr6`
173			`test_gr_immed 0x44444444,gr7`
174			`test_spr_immed 0x11111111,sr0 ; SGR4-7`
175			`test_spr_immed 0x22222222,sr1`
176			`test_spr_immed 0x33333333,sr2`
177			`test_spr_immed 0x44444444,sr3`
178
179			`set_spr_immed 0x55555555,sr0 ; SGR4-7`
180			`set_spr_immed 0x66666666,sr1`
181			`set_spr_immed 0x77777777,sr2`
182			`set_spr_immed 0x88888888,sr3`
183			`test_gr_immed 0x55555555,gr4 ; SGR4-7`
184			`test_gr_immed 0x66666666,gr5`
185			`test_gr_immed 0x77777777,gr6`
186			`test_gr_immed 0x88888888,gr7`
187			`test_spr_immed 0x55555555,sr0 ; SGR4-7`
188			`test_spr_immed 0x66666666,sr1`
189			`test_spr_immed 0x77777777,sr2`
190			`test_spr_immed 0x88888888,sr3`
191
192			`set_gr_immed 0x11111111,gr4 ; SGR4-7`
193			`set_gr_immed 0x22222222,gr5`
194			`set_gr_immed 0x33333333,gr6`
195			`set_gr_immed 0x44444444,gr7`
196			`test_gr_immed 0x11111111,gr4 ; SGR4-7`
197			`test_gr_immed 0x22222222,gr5`
198			`test_gr_immed 0x33333333,gr6`
199			`test_gr_immed 0x44444444,gr7`
200			`test_spr_immed 0x11111111,sr0 ; SGR4-7`
201			`test_spr_immed 0x22222222,sr1`
202			`test_spr_immed 0x33333333,sr2`
203			`test_spr_immed 0x44444444,sr3`
204			`rett 0`
205			`fail`