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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [mabshs.cgs] - Blame information for rev 24

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Line No. Rev Author Line
1 24 jeremybenn 
# frv testcase for mabshs $FRj,$FRk
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# mach: fr400
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        .include "testutils.inc"
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        start
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        .global mabshs
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mabshs:
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        set_fr_iimmed   0x0000,0x0000,fr10
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        mabshs          fr10,fr11
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        test_fr_limmed  0x0000,0x0000,fr11
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        set_fr_iimmed   0x0001,0xffff,fr10
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        mabshs          fr10,fr11
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        test_fr_limmed  0x0001,0x0001,fr11
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        set_fr_iimmed   0x7fff,0x8001,fr10
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        mabshs          fr10,fr11
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        test_fr_limmed  0x7fff,0x7fff,fr11
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        test_spr_bits   0x3c,2,0,msr0           ; msr0.sie is clear
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        test_spr_bits   2,1,0,msr0              ; msr0.ovf not set
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        test_spr_bits   1,0,0,msr0              ; msr0.aovf not set
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        test_spr_bits   0x7000,12,0,msr0        ; msr0.mtt not set
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        set_spr_immed   0,msr0
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        set_fr_iimmed   0x7fff,0x8000,fr10
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        mabshs          fr10,fr11
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        test_fr_limmed  0x7fff,0x7fff,fr11
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        test_spr_bits   0x3c,2,0x4,msr0         ; msr0.sie is set
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        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
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        set_spr_immed   0,msr0
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        set_fr_iimmed   0x8000,0x7fff,fr10
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        mabshs          fr10,fr11
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        test_fr_limmed  0x7fff,0x7fff,fr11
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        test_spr_bits   0x3c,2,0x8,msr0         ; msr0.sie is set
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        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
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        set_spr_immed   0,msr0
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        set_spr_immed   0,msr1
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        set_fr_iimmed   0x7fff,0x8000,fr10
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        set_fr_iimmed   0x8000,0x7fff,fr11
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        mabshs.p        fr10,fr12
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        mabshs          fr11,fr13
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        test_fr_limmed  0x7fff,0x7fff,fr12
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        test_fr_limmed  0x7fff,0x7fff,fr13
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        test_spr_bits   0x3c,2,0x4,msr0         ; msr0.sie is set
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        test_spr_bits   0x3c,2,0x8,msr1         ; msr1.sie is set
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        test_spr_bits   2,1,1,msr0              ; msr0.ovf set
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        test_spr_bits   2,1,1,msr1              ; msr1.ovf set
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        test_spr_bits   1,0,1,msr0              ; msr0.aovf set
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        test_spr_bits   0x7000,12,1,msr0        ; msr0.mtt set
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        pass

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