OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [mcop1.cgs] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# frv testcase for mcop1 $FRi,$FRj,$FRk
2
# mach: frv
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global mcop1
9
mcop1:
10
        mcop1.p         fr19,fr12,fr13  ; mp_exception: not-implemented
11
        mcop1           fr20,fr14,fr18  ; mp_exception: not-implemented
12
        test_spr_bits   0x7000,12,5,msr0; msr0.mtt is set
13
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
14
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
15
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
16
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
17
 
18
        mcop1.p         fr19,fr12,fr13  ; mp_exception: not-implemented
19
        mcop1           fr20,fr14,fr18  ; mp_exception: not-implemented
20
        test_spr_bits   0x7000,12,5,msr0; msr0.mtt is set
21
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
22
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
23
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
24
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
25
 
26
        mcop1           fr19,fr12,fr13  ; mp_exception: not-implemented
27
        test_spr_bits   0x7000,12,5,msr0; msr0.mtt is set
28
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
29
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
30
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
31
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
32
 
33
        mcop1           fr19,fr12,fr13  ; mp_exception: not-implemented
34
        test_spr_bits   0x7000,12,5,msr0; msr0.mtt is set
35
        test_spr_bits   0x003c,2,0,msr0 ; msr0.sie is clear
36
        test_spr_bits   0x0002,1,0,msr0 ; msr0.ovf is clear
37
        test_spr_bits   0x003c,2,0,msr1 ; msr1.sie is clear
38
        test_spr_bits   0x0002,1,0,msr1 ; msr1.ovf is clear
39
 
40
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.