OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [mmulhu.cgs] - Blame information for rev 272

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# frv testcase for mmulhu $GRi,$GRj,$GRk
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global mmulhu
9
mmulhu:
10
        set_fr_iimmed   3,2,fr7         ; multiply small numbers
11
        set_fr_iimmed   2,3,fr8
12
        mmulhu          fr7,fr8,acc0
13
        test_accg_immed         0,accg0
14
        test_acc_immed  6,acc0
15
        test_accg_immed         0,accg1
16
        test_acc_immed  6,acc1
17
 
18
        set_fr_iimmed   1,2,fr7         ; multiply by 1
19
        set_fr_iimmed   2,1,fr8
20
        mmulhu          fr7,fr8,acc0
21
        test_accg_immed         0,accg0
22
        test_acc_immed  2,acc0
23
        test_accg_immed         0,accg1
24
        test_acc_immed  2,acc1
25
 
26
        set_fr_iimmed   0,2,fr7         ; multiply by 0
27
        set_fr_iimmed   2,0,fr8
28
        mmulhu          fr7,fr8,acc0
29
        test_accg_immed         0,accg0
30
        test_acc_immed  0,acc0
31
        test_accg_immed         0,accg1
32
        test_acc_immed  0,acc1
33
 
34
        set_fr_iimmed   0x3fff,2,fr7    ; 15 bit result
35
        set_fr_iimmed   2,0x3fff,fr8
36
        mmulhu          fr7,fr8,acc0
37
        test_accg_immed         0,accg0
38
        test_acc_limmed 0x0000,0x7ffe,acc0
39
        test_accg_immed         0,accg1
40
        test_acc_limmed 0x0000,0x7ffe,acc1
41
 
42
        set_fr_iimmed   0x4000,2,fr7    ; 16 bit result
43
        set_fr_iimmed   2,0x4000,fr8
44
        mmulhu          fr7,fr8,acc0
45
        test_accg_immed         0,accg0
46
        test_acc_limmed 0x0000,0x8000,acc0
47
        test_accg_immed         0,accg1
48
        test_acc_limmed 0x0000,0x8000,acc1
49
 
50
        set_fr_iimmed   0x8000,2,fr7    ; 17 bit result
51
        set_fr_iimmed   2,0x8000,fr8
52
        mmulhu          fr7,fr8,acc0
53
        test_accg_immed         0,accg0
54
        test_acc_immed  0x00010000,acc0
55
        test_accg_immed         0,accg1
56
        test_acc_immed  0x00010000,acc1
57
 
58
        set_fr_iimmed   0x7fff,0x7fff,fr7       ; max positive result
59
        set_fr_iimmed   0x7fff,0x7fff,fr8
60
        mmulhu          fr7,fr8,acc0
61
        test_accg_immed         0,accg0
62
        test_acc_immed  0x3fff0001,acc0
63
        test_accg_immed         0,accg1
64
        test_acc_immed  0x3fff0001,acc1
65
 
66
        set_fr_iimmed   0x8000,0x8000,fr7       ; max positive result
67
        set_fr_iimmed   0x8000,0x8000,fr8
68
        mmulhu          fr7,fr8,acc0
69
        test_accg_immed         0,accg0
70
        test_acc_limmed 0x4000,0x0000,acc0
71
        test_accg_immed         0,accg1
72
        test_acc_limmed 0x4000,0x0000,acc1
73
 
74
        set_fr_iimmed   0xffff,0xffff,fr7       ; max positive result
75
        set_fr_iimmed   0xffff,0xffff,fr8
76
        mmulhu          fr7,fr8,acc0
77
        test_accg_immed         0,accg0
78
        test_acc_limmed 0xfffe,0x0001,acc0
79
        test_accg_immed         0,accg1
80
        test_acc_limmed 0xfffe,0x0001,acc1
81
 
82
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.