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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [nfsubs.cgs] - Blame information for rev 450

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Line No. Rev Author Line
1 24 jeremybenn 
# frv testcase for nfsubs $FRi,$FRj,$FRk
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# mach: fr500 fr550 frv
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        .include "testutils.inc"
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        float_constants
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        start
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        load_float_constants
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        .global nfsubs
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nfsubs:
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        nfsubs          fr0,fr16,fr1
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        test_fr_fr      fr1,fr0
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr4,fr16,fr1
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        test_fr_fr      fr1,fr4
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr8,fr16,fr1
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        test_fr_fr      fr1,fr8
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr12,fr16,fr1
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        test_fr_fr      fr1,fr12
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr16,fr16,fr1
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        test_fr_fr      fr1,fr16
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        test_fr_fr      fr1,fr20
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr20,fr16,fr1
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        test_fr_fr      fr1,fr16
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        test_fr_fr      fr1,fr20
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr24,fr16,fr1
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        test_fr_fr      fr1,fr24
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr28,fr16,fr1
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        test_fr_fr      fr1,fr28
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr32,fr16,fr1
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        test_fr_fr      fr1,fr32
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr36,fr16,fr1
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        test_fr_fr      fr1,fr36
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr40,fr16,fr1
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        test_fr_fr      fr1,fr40
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr44,fr16,fr1
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        test_fr_fr      fr1,fr44
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr48,fr16,fr1
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        test_fr_fr      fr1,fr48
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr52,fr16,fr1
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        test_fr_fr      fr1,fr52
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr0,fr20,fr1
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        test_fr_fr      fr1,fr0
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr4,fr20,fr1
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        test_fr_fr      fr1,fr4
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr8,fr20,fr1
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        test_fr_fr      fr1,fr8
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr12,fr20,fr1
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        test_fr_fr      fr1,fr12
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr16,fr20,fr1
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        test_fr_fr      fr1,fr16
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        test_fr_fr      fr1,fr20
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr20,fr20,fr1
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        test_fr_fr      fr1,fr16
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        test_fr_fr      fr1,fr20
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr24,fr20,fr1
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        test_fr_fr      fr1,fr24
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr28,fr20,fr1
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        test_fr_fr      fr1,fr28
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr32,fr20,fr1
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        test_fr_fr      fr1,fr32
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr36,fr20,fr1
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        test_fr_fr      fr1,fr36
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr40,fr20,fr1
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        test_fr_fr      fr1,fr40
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr44,fr20,fr1
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        test_fr_fr      fr1,fr44
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr48,fr20,fr1
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        test_fr_fr      fr1,fr48
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr52,fr20,fr1
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        test_fr_fr      fr1,fr52
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr32,fr36,fr1
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        test_fr_fr      fr1,fr8
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr44,fr40,fr1
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        test_fr_fr      fr1,fr36
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        ; try to cause exceptions
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        nfsubs          fr4,fr28,fr1
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;       test_fr_fr      fr1,fr44
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr0,fr28,fr1
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;       test_fr_fr      fr1,fr44
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr56,fr28,fr1
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;       test_fr_fr      fr1,fr44
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        test_spr_immed  0,fner1
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        test_spr_immed  0,fner0
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        nfsubs          fr60,fr28,fr1
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;       test_fr_fr      fr1,fr44
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        test_spr_immed  2,fner1
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        test_spr_immed  0,fner0
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        pass
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