OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [tlt.cgs] - Blame information for rev 157

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# frv testcase for tlt $ICCi_2,$GRi,$GRj
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global tlt
9
tlt:
10
        and_spr_immed   -4081,tbr               ; clear tbr.tt
11
        set_gr_spr      tbr,gr7
12
        inc_gr_immed    2112,gr7                ; address of exception handler
13
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
14
 
15
        set_spr_immed   128,lcr
16
        set_gr_immed    0,gr7
17
        set_gr_immed    4,gr8
18
 
19
        set_spr_addr    bad,lr
20
        set_icc         0x0 0
21
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
22
 
23
        set_spr_addr    bad,lr
24
        set_icc         0x1 0
25
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
26
 
27
        set_psr_et      1
28
        set_spr_addr    ok2,lr
29
        set_icc         0x2 0
30
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
31
        fail
32
ok2:
33
        set_psr_et      1
34
        set_spr_addr    ok3,lr
35
        set_icc         0x3 0
36
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
37
        fail
38
ok3:
39
        set_spr_addr    bad,lr
40
        set_icc         0x4 0
41
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
42
 
43
        set_spr_addr    bad,lr
44
        set_icc         0x5 0
45
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
46
 
47
        set_psr_et      1
48
        set_spr_addr    ok6,lr
49
        set_icc         0x6 0
50
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
51
        fail
52
ok6:
53
        set_psr_et      1
54
        set_spr_addr    ok7,lr
55
        set_icc         0x7 0
56
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
57
        fail
58
ok7:
59
        set_psr_et      1
60
        set_spr_addr    ok8,lr
61
        set_icc         0x8 0
62
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
63
        fail
64
ok8:
65
        set_psr_et      1
66
        set_spr_addr    ok9,lr
67
        set_icc         0x9 0
68
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
69
        fail
70
ok9:
71
        set_spr_addr    bad,lr
72
        set_icc         0xa 0
73
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
74
 
75
        set_spr_addr    bad,lr
76
        set_icc         0xb 0
77
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
78
 
79
        set_psr_et      1
80
        set_spr_addr    okc,lr
81
        set_icc         0xc 0
82
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
83
        fail
84
okc:
85
        set_psr_et      1
86
        set_spr_addr    okd,lr
87
        set_icc         0xd 0
88
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
89
        fail
90
okd:
91
        set_spr_addr    bad,lr
92
        set_icc         0xe 0
93
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
94
 
95
        set_spr_addr    bad,lr
96
        set_icc         0xf 0
97
        tlt             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
98
 
99
        pass
100
bad:
101
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.