OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [frv/] [tne.cgs] - Blame information for rev 225

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn
# frv testcase for tne $ICCi_2,$GRi,$GRj
2
# mach: all
3
 
4
        .include "testutils.inc"
5
 
6
        start
7
 
8
        .global tne
9
tne:
10
        and_spr_immed   -4081,tbr               ; clear tbr.tt
11
        set_gr_spr      tbr,gr7
12
        inc_gr_immed    2112,gr7                ; address of exception handler
13
        set_bctrlr_0_0  gr7     ; bctrlr 0,0
14
 
15
        set_spr_immed   128,lcr
16
        set_gr_immed    0,gr7
17
        set_gr_immed    4,gr8
18
 
19
        set_psr_et      1
20
        set_spr_addr    ok0,lr
21
        set_icc         0x0 0
22
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
23
        fail
24
ok0:
25
        set_psr_et      1
26
        set_spr_addr    ok1,lr
27
        set_icc         0x1 0
28
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
29
        fail
30
ok1:
31
        set_psr_et      1
32
        set_spr_addr    ok2,lr
33
        set_icc         0x2 0
34
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
35
        fail
36
ok2:
37
        set_psr_et      1
38
        set_spr_addr    ok3,lr
39
        set_icc         0x3 0
40
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
41
        fail
42
ok3:
43
        set_spr_addr    bad,lr
44
        set_icc         0x4 0
45
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
46
 
47
        set_spr_addr    bad,lr
48
        set_icc         0x5 0
49
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
50
 
51
        set_spr_addr    bad,lr
52
        set_icc         0x6 0
53
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
54
 
55
        set_spr_addr    bad,lr
56
        set_icc         0x7 0
57
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
58
 
59
        set_psr_et      1
60
        set_spr_addr    ok8,lr
61
        set_icc         0x8 0
62
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
63
        fail
64
ok8:
65
        set_psr_et      1
66
        set_spr_addr    ok9,lr
67
        set_icc         0x9 0
68
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
69
        fail
70
ok9:
71
        set_psr_et      1
72
        set_spr_addr    oka,lr
73
        set_icc         0xa 0
74
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
75
        fail
76
oka:
77
        set_psr_et      1
78
        set_spr_addr    okb,lr
79
        set_icc         0xb 0
80
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
81
        fail
82
okb:
83
        set_spr_addr    bad,lr
84
        set_icc         0xc 0
85
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
86
 
87
        set_spr_addr    bad,lr
88
        set_icc         0xd 0
89
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
90
 
91
        set_spr_addr    bad,lr
92
        set_icc         0xe 0
93
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
94
 
95
        set_spr_addr    bad,lr
96
        set_icc         0xf 0
97
        tne             icc0,gr7,gr8    ; should branch to tbr + (128 + 4)*16
98
 
99
        pass
100
bad:
101
        fail

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.