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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [addb.s] - Blame information for rev 225

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1 24 jeremybenn
# Hitachi H8 testcase 'add.b'
2
# mach(): all
3
# as(h8300):    --defsym sim_cpu=0
4
# as(h8300h):   --defsym sim_cpu=1
5
# as(h8300s):   --defsym sim_cpu=2
6
# as(h8sx):     --defsym sim_cpu=3
7
# ld(h8300h):   -m h8300helf
8
# ld(h8300s):   -m h8300self
9
# ld(h8sx):     -m h8300sxelf
10
 
11
        .include "testutils.inc"
12
 
13
        # Instructions tested:
14
        # add.b #xx:8, rd       ;                     8   rd xxxxxxxx
15
        # add.b #xx:8, @erd     ;         7 d rd ???? 8 ???? xxxxxxxx
16
        # add.b #xx:8, @erd+    ; 0 1 7 4 6 c rd 1??? 8 ???? xxxxxxxx
17
        # add.b #xx:8, @erd-    ; 0 1 7 6 6 c rd 1??? 8 ???? xxxxxxxx
18
        # add.b #xx:8, @+erd    ; 0 1 7 5 6 c rd 1??? 8 ???? xxxxxxxx
19
        # add.b #xx:8, @-erd    ; 0 1 7 7 6 c rd 1??? 8 ???? xxxxxxxx
20
        # add.b #xx:8, @(d:16, erd)     ; 0 1 7 4 6 e b30 | rd, b31, dd:16 8 ???? xxxxxxxx
21
        # add.b #xx:8, @(d:32, erd)     ; 7 8 b30 | rd, 4 6 a 2 8 dd:32 8 ???? xxxxxxxx
22
        # add.b #xx:8, @aa:8            ; 7 f aaaaaaaa 8 ???? xxxxxxxx
23
        # add.b #xx:8, @aa:16           ; 6 a 1 1??? aa:16 8 ???? xxxxxxxx
24
        # add.b #xx:8, @aa:32           ; 6 a 3 1??? aa:32 8 ???? xxxxxxxx
25
        # add.b rs, rd          ;                     0 8 rs rd
26
        # add.b reg8, @erd      ;         7 d rd ???? 0 8 rs ????
27
        # add.b reg8, @erd+     ;         0 1 7     9 8 rd 1 rs
28
        # add.b reg8, @erd-     ;         0 1 7     9 a rd 1 rs
29
        # add.b reg8, @+erd     ;         0 1 7     9 9 rd 1 rs
30
        # add.b reg8, @-erd     ;         0 1 7     9 b rd 1 rs
31
        # add.b reg8, @(d:16, erd)      ; 0 1 7 9 c b30 | rd32, 1 rs8 imm16
32
        # add.b reg8, @(d:32, erd)      ; 0 1 7 9 d b31 | rd32, 1 rs8 imm32
33
        # add.b reg8, @aa:8             ; 7 f aaaaaaaa 0 8 rs ????
34
        # add.b reg8, @aa:16            ; 6 a 1 1??? aa:16 0 8 rs ????
35
        # add.b reg8, @aa:32            ; 6 a 3 1??? aa:32 0 8 rs ????
36
        #
37
 
38
        # Coming soon:
39
        # add.b #xx:8, @(d:2, erd)      ; 0 1 7 b30 | b21 | dd:2,  8 ???? xxxxxxxx
40
        # add.b reg8, @(d:2, erd)       ; 0 1 7 9 dd:2 rd32 1 rs8
41
        # ...
42
 
43
.data
44
pre_byte:       .byte 0
45
byte_dest:      .byte 0
46
post_byte:      .byte 0
47
 
48
        start
49
 
50
add_b_imm8_reg:
51
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
52
        ;;  fixme set ccr
53
 
54
        ;;  add.b #xx:8,Rd
55
        add.b   #5:8, r0l       ; Immediate 8-bit src, reg8 dst
56
 
57
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
58
        test_h_gr16 0xa5aa r0   ; add result:   a5 + 5
59
.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
60
        test_h_gr32 0xa5a5a5aa er0      ; add result:    a5 + 5
61
.endif
62
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
63
        test_gr_a5a5 2
64
        test_gr_a5a5 3
65
        test_gr_a5a5 4
66
        test_gr_a5a5 5
67
        test_gr_a5a5 6
68
        test_gr_a5a5 7
69
 
70
.if (sim_cpu == h8sx)
71
add_b_imm8_rdind:
72
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
73
        set_ccr_zero
74
 
75
        ;;  add.b #xx:8,@eRd
76
        mov     #byte_dest, er0
77
        add.b   #5:8, @er0      ; Immediate 8-bit src, reg indirect dst
78
;;;     .word   0x7d00
79
;;;     .word   0x8005
80
 
81
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
82
        test_ovf_clear
83
        test_zero_clear
84
        test_neg_clear
85
 
86
        test_h_gr32 byte_dest, er0      ; er0 still contains address
87
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
88
        test_gr_a5a5 2
89
        test_gr_a5a5 3
90
        test_gr_a5a5 4
91
        test_gr_a5a5 5
92
        test_gr_a5a5 6
93
        test_gr_a5a5 7
94
 
95
        ;; Now check the result of the add to memory.
96
        sub.b   r0l, r0l
97
        mov.b   @byte_dest, r0l
98
        cmp.b   #5, r0l
99
        beq     .L1
100
        fail
101
.L1:
102
 
103
add_b_imm8_rdpostinc:
104
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
105
        set_ccr_zero
106
 
107
        ;;  add.b #xx:8,@eRd+
108
        mov     #byte_dest, er0
109
        add.b   #5:8, @er0+     ; Immediate 8-bit src, reg post-inc dst
110
;;;     .word   0x0174
111
;;;     .word   0x6c08
112
;;;     .word   0x8005
113
 
114
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
115
        test_ovf_clear
116
        test_zero_clear
117
        test_neg_clear
118
 
119
        test_h_gr32 post_byte, er0      ; er0 contains address plus one
120
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
121
        test_gr_a5a5 2
122
        test_gr_a5a5 3
123
        test_gr_a5a5 4
124
        test_gr_a5a5 5
125
        test_gr_a5a5 6
126
        test_gr_a5a5 7
127
 
128
        ;; Now check the result of the add to memory.
129
        sub.b   r0l, r0l
130
        mov.b   @byte_dest, r0l
131
        cmp.b   #10, r0l
132
        beq     .L2
133
        fail
134
.L2:
135
 
136
add_b_imm8_rdpostdec:
137
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
138
        set_ccr_zero
139
 
140
        ;;  add.b #xx:8,@eRd-
141
        mov     #byte_dest, er0
142
        add.b   #5:8, @er0-     ; Immediate 8-bit src, reg post-dec dst
143
;;;     .word   0x0176
144
;;;     .word   0x6c08
145
;;;     .word   0x8005
146
 
147
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
148
        test_ovf_clear
149
        test_zero_clear
150
        test_neg_clear
151
 
152
        test_h_gr32 pre_byte, er0       ; er0 contains address minus one
153
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
154
        test_gr_a5a5 2
155
        test_gr_a5a5 3
156
        test_gr_a5a5 4
157
        test_gr_a5a5 5
158
        test_gr_a5a5 6
159
        test_gr_a5a5 7
160
 
161
        ;; Now check the result of the add to memory.
162
        sub.b   r0l, r0l
163
        mov.b   @byte_dest, r0l
164
        cmp.b   #15, r0l
165
        beq     .L3
166
        fail
167
.L3:
168
 
169
add_b_imm8_rdpreinc:
170
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
171
        set_ccr_zero
172
 
173
        ;;  add.b #xx:8,@+eRd
174
        mov     #pre_byte, er0
175
        add.b   #5:8, @+er0     ; Immediate 8-bit src, reg pre-inc dst
176
;;;     .word   0x0175
177
;;;     .word   0x6c08
178
;;;     .word   0x8005
179
 
180
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
181
        test_ovf_clear
182
        test_zero_clear
183
        test_neg_clear
184
 
185
        test_h_gr32 byte_dest, er0      ; er0 contains destination address 
186
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
187
        test_gr_a5a5 2
188
        test_gr_a5a5 3
189
        test_gr_a5a5 4
190
        test_gr_a5a5 5
191
        test_gr_a5a5 6
192
        test_gr_a5a5 7
193
 
194
        ;; Now check the result of the add to memory.
195
        sub.b   r0l, r0l
196
        mov.b   @byte_dest, r0l
197
        cmp.b   #20, r0l
198
        beq     .L4
199
        fail
200
.L4:
201
 
202
add_b_imm8_rdpredec:
203
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
204
        set_ccr_zero
205
 
206
        ;;  add.b #xx:8,@-eRd
207
        mov     #post_byte, er0
208
        add.b   #5:8, @-er0     ; Immediate 8-bit src, reg pre-dec dst
209
;;;     .word   0x0177
210
;;;     .word   0x6c08
211
;;;     .word   0x8005
212
 
213
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
214
        test_ovf_clear
215
        test_zero_clear
216
        test_neg_clear
217
 
218
        test_h_gr32 byte_dest, er0      ; er0 contains destination address 
219
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
220
        test_gr_a5a5 2
221
        test_gr_a5a5 3
222
        test_gr_a5a5 4
223
        test_gr_a5a5 5
224
        test_gr_a5a5 6
225
        test_gr_a5a5 7
226
 
227
        ;; Now check the result of the add to memory.
228
        sub.b   r0l, r0l
229
        mov.b   @byte_dest, r0l
230
        cmp.b   #25, r0l
231
        beq     .L5
232
        fail
233
.L5:
234
 
235
add_b_imm8_disp16:
236
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
237
        set_ccr_zero
238
 
239
        ;;  add.b #xx:8,@(dd:16, eRd)
240
        mov     #post_byte, er0
241
        add.b   #5:8, @(-1:16, er0)     ; Immediate 8-bit src, 16-bit reg disp dest.
242
;;;     .word   0x0174
243
;;;     .word   0x6e08
244
;;;     .word   0xffff
245
;;;     .word   0x8005
246
 
247
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
248
        test_ovf_clear
249
        test_zero_clear
250
        test_neg_clear
251
 
252
        test_h_gr32   post_byte, er0    ; er0 contains address plus one
253
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
254
        test_gr_a5a5 2
255
        test_gr_a5a5 3
256
        test_gr_a5a5 4
257
        test_gr_a5a5 5
258
        test_gr_a5a5 6
259
        test_gr_a5a5 7
260
 
261
        ;; Now check the result of the add to memory.
262
        sub.b   r0l, r0l
263
        mov.b   @byte_dest, r0l
264
        cmp.b   #30, r0l
265
        beq     .L6
266
        fail
267
.L6:
268
 
269
add_b_imm8_disp32:
270
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
271
        set_ccr_zero
272
 
273
        ;;  add.b #xx:8,@(dd:32, eRd)
274
        mov     #pre_byte, er0
275
        add.b   #5:8, @(1:32, er0)      ; Immediate 8-bit src, 32-bit reg disp. dest.
276
;;;     .word   0x7804
277
;;;     .word   0x6a28
278
;;;     .word   0x0000
279
;;;     .word   0x0001
280
;;;     .word   0x8005
281
 
282
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
283
        test_ovf_clear
284
        test_zero_clear
285
        test_neg_clear
286
 
287
        test_h_gr32 pre_byte, er0       ; er0 contains address minus one
288
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
289
        test_gr_a5a5 2
290
        test_gr_a5a5 3
291
        test_gr_a5a5 4
292
        test_gr_a5a5 5
293
        test_gr_a5a5 6
294
        test_gr_a5a5 7
295
 
296
        ;; Now check the result of the add to memory.
297
        sub.b   r0l, r0l
298
        mov.b   @byte_dest, r0l
299
        cmp.b   #35, r0l
300
        beq     .L7
301
        fail
302
.L7:
303
 
304
add_b_imm8_abs8:
305
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
306
        set_ccr_zero
307
 
308
        ;;  add.b reg8,@aa:8
309
        ;; NOTE: for abs8, we will use the SBR register as a base,
310
        ;; since otherwise we would have to make sure that the destination
311
        ;; was in the zero page.
312
        ;;
313
        mov     #byte_dest-100, er0
314
        ldc     er0, sbr
315
        add.b   #5, @100:8      ; 8-bit reg src, 8-bit absolute dest
316
;;;     .word   0x7f64
317
;;;     .word   0x8005
318
 
319
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
320
        test_ovf_clear
321
        test_zero_clear
322
        test_neg_clear
323
 
324
        test_h_gr32  byte_dest-100, er0 ; reg 0 has base address
325
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
326
        test_gr_a5a5 2
327
        test_gr_a5a5 3
328
        test_gr_a5a5 4
329
        test_gr_a5a5 5
330
        test_gr_a5a5 6
331
        test_gr_a5a5 7
332
 
333
        ;; Now check the result of the add to memory.
334
        sub.b   r0l, r0l
335
        mov.b   @byte_dest, r0l
336
        cmp.b   #40, r0l
337
        beq     .L8
338
        fail
339
.L8:
340
 
341
add_b_imm8_abs16:
342
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
343
        set_ccr_zero
344
 
345
        ;;  add.b #xx:8,@aa:16
346
        add.b   #5:8, @byte_dest:16     ; Immediate 8-bit src, 16-bit absolute dest
347
;;;     .word   0x6a18
348
;;;     .word   byte_dest
349
;;;     .word   0x8005
350
 
351
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
352
        test_ovf_clear
353
        test_zero_clear
354
        test_neg_clear
355
 
356
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
357
        test_gr_a5a5 1
358
        test_gr_a5a5 2
359
        test_gr_a5a5 3
360
        test_gr_a5a5 4
361
        test_gr_a5a5 5
362
        test_gr_a5a5 6
363
        test_gr_a5a5 7
364
 
365
        ;; Now check the result of the add to memory.
366
        sub.b   r0l, r0l
367
        mov.b   @byte_dest, r0l
368
        cmp.b   #45, r0l
369
        beq     .L9
370
        fail
371
.L9:
372
 
373
add_b_imm8_abs32:
374
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
375
        set_ccr_zero
376
 
377
        ;;  add.b #xx:8,@aa:32
378
        add.b   #5:8, @byte_dest:32     ; Immediate 8-bit src, 32-bit absolute dest
379
;;;     .word   0x6a38
380
;;;     .long   byte_dest
381
;;;     .word   0x8005
382
 
383
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
384
        test_ovf_clear
385
        test_zero_clear
386
        test_neg_clear
387
 
388
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
389
        test_gr_a5a5 1
390
        test_gr_a5a5 2
391
        test_gr_a5a5 3
392
        test_gr_a5a5 4
393
        test_gr_a5a5 5
394
        test_gr_a5a5 6
395
        test_gr_a5a5 7
396
 
397
        ;; Now check the result of the add to memory.
398
        sub.b   r0l, r0l
399
        mov.b   @byte_dest, r0l
400
        cmp.b   #50, r0l
401
        beq     .L10
402
        fail
403
.L10:
404
 
405
.endif
406
 
407
add_b_reg8_reg8:
408
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
409
        ;;  fixme set ccr
410
 
411
        ;;  add.b Rs,Rd
412
        mov.b   #5, r0h
413
        add.b   r0h, r0l        ; Register operand
414
 
415
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
416
        test_h_gr16 0x05aa r0   ; add result:   a5 + 5
417
.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
418
        test_h_gr32 0xa5a505aa er0      ; add result:   a5 + 5
419
.endif
420
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
421
        test_gr_a5a5 2
422
        test_gr_a5a5 3
423
        test_gr_a5a5 4
424
        test_gr_a5a5 5
425
        test_gr_a5a5 6
426
        test_gr_a5a5 7
427
 
428
.if (sim_cpu == h8sx)
429
add_b_reg8_rdind:
430
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
431
        set_ccr_zero
432
 
433
        ;;  add.b rs8,@eRd      ; Add to register indirect
434
        mov     #byte_dest, er0
435
        mov     #5, r1l
436
        add.b   r1l, @er0       ; reg8 src, reg indirect dest
437
;;;     .word   0x7d00
438
;;;     .word   0x0890
439
 
440
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
441
        test_ovf_clear
442
        test_zero_clear
443
        test_neg_clear
444
 
445
        test_h_gr32 byte_dest er0       ; er0 still contains address
446
        test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
447
 
448
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
449
        test_gr_a5a5 3
450
        test_gr_a5a5 4
451
        test_gr_a5a5 5
452
        test_gr_a5a5 6
453
        test_gr_a5a5 7
454
 
455
        ;; Now check the result of the add to memory.
456
        sub.b   r0l, r0l
457
        mov.b   @byte_dest, r0l
458
        cmp.b   #55, r0l
459
        beq     .L11
460
        fail
461
.L11:
462
 
463
add_b_reg8_rdpostinc:
464
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
465
        set_ccr_zero
466
 
467
        ;;  add.b rs8,@eRd+     ; Add to register post-increment
468
        mov     #byte_dest, er0
469
        mov     #5, r1l
470
        add.b   r1l, @er0+      ; reg8 src, reg post-incr dest
471
;;;     .word   0x0179
472
;;;     .word   0x8019
473
 
474
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
475
        test_ovf_clear
476
        test_zero_clear
477
        test_neg_clear
478
 
479
        test_h_gr32 post_byte er0       ; er0 contains address plus one
480
        test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
481
 
482
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
483
        test_gr_a5a5 3
484
        test_gr_a5a5 4
485
        test_gr_a5a5 5
486
        test_gr_a5a5 6
487
        test_gr_a5a5 7
488
 
489
        ;; Now check the result of the add to memory.
490
        sub.b   r0l, r0l
491
        mov.b   @byte_dest, r0l
492
        cmp.b   #60, r0l
493
        beq     .L12
494
        fail
495
.L12:
496
 
497
add_b_reg8_rdpostdec:
498
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
499
        set_ccr_zero
500
 
501
        ;;  add.b rs8,@eRd-     ; Add to register post-decrement
502
        mov     #byte_dest, er0
503
        mov     #5, r1l
504
        add.b   r1l, @er0-      ; reg8 src, reg post-decr dest
505
;;;     .word   0x0179
506
;;;     .word   0xa019
507
 
508
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
509
        test_ovf_clear
510
        test_zero_clear
511
        test_neg_clear
512
 
513
        test_h_gr32 pre_byte er0        ; er0 contains address minus one
514
        test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
515
 
516
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
517
        test_gr_a5a5 3
518
        test_gr_a5a5 4
519
        test_gr_a5a5 5
520
        test_gr_a5a5 6
521
        test_gr_a5a5 7
522
 
523
        ;; Now check the result of the add to memory.
524
        sub.b   r0l, r0l
525
        mov.b   @byte_dest, r0l
526
        cmp.b   #65, r0l
527
        beq     .L13
528
        fail
529
.L13:
530
 
531
add_b_reg8_rdpreinc:
532
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
533
        set_ccr_zero
534
 
535
        ;;  add.b rs8,@+eRd     ; Add to register pre-increment
536
        mov     #pre_byte, er0
537
        mov     #5, r1l
538
        add.b   r1l, @+er0      ; reg8 src, reg pre-incr dest
539
;;;     .word   0x0179
540
;;;     .word   0x9019
541
 
542
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
543
        test_ovf_clear
544
        test_zero_clear
545
        test_neg_clear
546
 
547
        test_h_gr32 byte_dest er0       ; er0 contains destination address 
548
        test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
549
 
550
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
551
        test_gr_a5a5 3
552
        test_gr_a5a5 4
553
        test_gr_a5a5 5
554
        test_gr_a5a5 6
555
        test_gr_a5a5 7
556
 
557
        ;; Now check the result of the add to memory.
558
        sub.b   r0l, r0l
559
        mov.b   @byte_dest, r0l
560
        cmp.b   #70, r0l
561
        beq     .L14
562
        fail
563
.L14:
564
 
565
add_b_reg8_rdpredec:
566
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
567
        set_ccr_zero
568
 
569
        ;;  add.b rs8,@-eRd     ; Add to register pre-decrement
570
        mov     #post_byte, er0
571
        mov     #5, r1l
572
        add.b   r1l, @-er0      ; reg8 src, reg pre-decr dest
573
;;;     .word   0x0179
574
;;;     .word   0xb019
575
 
576
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
577
        test_ovf_clear
578
        test_zero_clear
579
        test_neg_clear
580
 
581
        test_h_gr32 byte_dest er0       ; er0 contains destination address 
582
        test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
583
 
584
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
585
        test_gr_a5a5 3
586
        test_gr_a5a5 4
587
        test_gr_a5a5 5
588
        test_gr_a5a5 6
589
        test_gr_a5a5 7
590
 
591
        ;; Now check the result of the add to memory.
592
        sub.b   r0l, r0l
593
        mov.b   @byte_dest, r0l
594
        cmp.b   #75, r0l
595
        beq     .L15
596
        fail
597
.L15:
598
 
599
add_b_reg8_disp16:
600
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
601
        set_ccr_zero
602
 
603
        ;;  add.b rs8,@(dd:16, eRd)     ; Add to register + 16-bit displacement
604
        mov     #pre_byte, er0
605
        mov     #5, r1l
606
        add.b   r1l, @(1:16, er0)       ; reg8 src, 16-bit reg disp dest
607
;;;     .word   0x0179
608
;;;     .word   0xc019
609
;;;     .word   0x0001
610
 
611
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
612
        test_ovf_clear
613
        test_zero_clear
614
        test_neg_clear
615
 
616
        test_h_gr32 pre_byte er0        ; er0 contains address minus one
617
        test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
618
 
619
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
620
        test_gr_a5a5 3
621
        test_gr_a5a5 4
622
        test_gr_a5a5 5
623
        test_gr_a5a5 6
624
        test_gr_a5a5 7
625
 
626
        ;; Now check the result of the add to memory.
627
        sub.b   r0l, r0l
628
        mov.b   @byte_dest, r0l
629
        cmp.b   #80, r0l
630
        beq     .L16
631
        fail
632
.L16:
633
 
634
add_b_reg8_disp32:
635
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
636
        set_ccr_zero
637
 
638
        ;;  add.b rs8,@-eRd     ; Add to register plus 32-bit displacement
639
        mov     #post_byte, er0
640
        mov     #5, r1l
641
        add.b   r1l, @(-1:32, er0)      ; reg8 src, 32-bit reg disp dest
642
;;;     .word   0x0179
643
;;;     .word   0xd819
644
;;;     .word   0xffff
645
;;;     .word   0xffff
646
 
647
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
648
        test_ovf_clear
649
        test_zero_clear
650
        test_neg_clear
651
 
652
        test_h_gr32 post_byte er0       ; er0 contains address plus one
653
        test_h_gr32 0xa5a5a505 er1      ; er1 has the test load
654
 
655
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
656
        test_gr_a5a5 3
657
        test_gr_a5a5 4
658
        test_gr_a5a5 5
659
        test_gr_a5a5 6
660
        test_gr_a5a5 7
661
 
662
        ;; Now check the result of the add to memory.
663
        sub.b   r0l, r0l
664
        mov.b   @byte_dest, r0l
665
        cmp.b   #85, r0l
666
        beq     .L17
667
        fail
668
.L17:
669
 
670
add_b_reg8_abs8:
671
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
672
        set_ccr_zero
673
 
674
        ;;  add.b reg8,@aa:8
675
        ;; NOTE: for abs8, we will use the SBR register as a base,
676
        ;; since otherwise we would have to make sure that the destination
677
        ;; was in the zero page.
678
        ;;
679
        mov     #byte_dest-100, er0
680
        ldc     er0, sbr
681
        mov     #5, r1l
682
        add.b   r1l, @100:8     ; 8-bit reg src, 8-bit absolute dest
683
;;;     .word   0x7f64
684
;;;     .word   0x0890
685
 
686
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
687
        test_ovf_clear
688
        test_zero_clear
689
        test_neg_clear
690
 
691
        test_h_gr32  byte_dest-100, er0 ; reg 0 has base address
692
        test_h_gr32  0xa5a5a505 er1     ; reg 1 has test load
693
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
694
        test_gr_a5a5 3
695
        test_gr_a5a5 4
696
        test_gr_a5a5 5
697
        test_gr_a5a5 6
698
        test_gr_a5a5 7
699
 
700
        ;; Now check the result of the add to memory.
701
        sub.b   r0l, r0l
702
        mov.b   @byte_dest, r0l
703
        cmp.b   #90, r0l
704
        beq     .L18
705
        fail
706
.L18:
707
 
708
add_b_reg8_abs16:
709
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
710
        set_ccr_zero
711
 
712
        ;;  add.b reg8,@aa:16
713
        mov     #5, r0l
714
        add.b   r0l, @byte_dest:16      ; 8-bit reg src, 16-bit absolute dest
715
;;;     .word   0x6a18
716
;;;     .word   byte_dest
717
;;;     .word   0x0880
718
 
719
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
720
        test_ovf_clear
721
        test_zero_clear
722
        test_neg_clear
723
 
724
        test_h_gr32  0xa5a5a505 er0     ; reg 0 has test load
725
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
726
        test_gr_a5a5 2
727
        test_gr_a5a5 3
728
        test_gr_a5a5 4
729
        test_gr_a5a5 5
730
        test_gr_a5a5 6
731
        test_gr_a5a5 7
732
 
733
        ;; Now check the result of the add to memory.
734
        sub.b   r0l, r0l
735
        mov.b   @byte_dest, r0l
736
        cmp.b   #95, r0l
737
        beq     .L19
738
        fail
739
.L19:
740
 
741
add_b_reg8_abs32:
742
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
743
        set_ccr_zero
744
 
745
        ;;  add.b reg8,@aa:32
746
        mov     #5, r0l
747
        add.b   r0l, @byte_dest:32      ; 8-bit reg src, 32-bit absolute dest
748
;;;     .word   0x6a38
749
;;;     .long   byte_dest
750
;;;     .word   0x0880
751
 
752
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
753
        test_ovf_clear
754
        test_zero_clear
755
        test_neg_clear
756
 
757
        test_h_gr32  0xa5a5a505 er0     ; reg 0 has test load
758
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
759
        test_gr_a5a5 2
760
        test_gr_a5a5 3
761
        test_gr_a5a5 4
762
        test_gr_a5a5 5
763
        test_gr_a5a5 6
764
        test_gr_a5a5 7
765
 
766
        ;; Now check the result of the add to memory.
767
        sub.b   r0l, r0l
768
        mov.b   @byte_dest, r0l
769
        cmp.b   #100, r0l
770
        beq     .L20
771
        fail
772
.L20:
773
 
774
.endif
775
 
776
        pass
777
 
778
        exit 0

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