OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [allinsn.exp] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
# Hitachi H8/300 (h, s, sx) simulator testsuite
2 
 
3 
set all "h8300 h8300h h8300s h8sx"
4 
 
5 
if {[istarget h8300*-*-*] || [istarget h8sx*-*-*]} then {
6 
    run_sim_test addb.s  $all
7 
    run_sim_test addw.s  $all
8 
    run_sim_test addl.s  $all
9 
    run_sim_test adds.s  $all
10 
    run_sim_test addx.s  $all
11 
    run_sim_test andb.s  $all
12 
    run_sim_test andw.s  $all
13 
    run_sim_test andl.s  $all
14 
    run_sim_test band.s  $all
15 
    run_sim_test bfld.s  h8sx
16 
    run_sim_test biand.s $all
17 
    run_sim_test bra.s   $all
18 
    run_sim_test bset.s  $all
19 
    run_sim_test cmpb.s  $all
20 
    run_sim_test cmpw.s  $all
21 
    run_sim_test cmpl.s  $all
22 
    run_sim_test daa.s   $all
23 
    run_sim_test das.s   $all
24 
    run_sim_test dec.s   $all
25 
    run_sim_test div.s   $all
26 
    run_sim_test extw.s  $all
27 
    run_sim_test extl.s  $all
28 
    run_sim_test inc.s   $all
29 
    run_sim_test jmp.s   $all
30 
    run_sim_test ldc.s   $all
31 
    run_sim_test ldm.s   $all
32 
    run_sim_test mac.s   $all
33 
    run_sim_test movb.s  $all
34 
    run_sim_test movw.s  $all
35 
    run_sim_test movl.s  $all
36 
    run_sim_test mova.s  h8sx
37 
    run_sim_test movmd.s h8sx
38 
    run_sim_test movsd.s h8sx
39 
    run_sim_test mul.s   $all
40 
    run_sim_test neg.s   $all
41 
    run_sim_test nop.s   $all
42 
    run_sim_test not.s   $all
43 
    run_sim_test orb.s   $all
44 
    run_sim_test orw.s   $all
45 
    run_sim_test orl.s   $all
46 
    run_sim_test rotl.s  $all
47 
    run_sim_test rotr.s  $all
48 
    run_sim_test rotxl.s $all
49 
    run_sim_test rotxr.s $all
50 
    run_sim_test shal.s  $all
51 
    run_sim_test shar.s  $all
52 
    run_sim_test shll.s  $all
53 
    run_sim_test shlr.s  $all
54 
    run_sim_test stack.s $all
55 
    run_sim_test stc.s   $all
56 
    run_sim_test subb.s  $all
57 
    run_sim_test subw.s  $all
58 
    run_sim_test subl.s  $all
59 
    run_sim_test subs.s  $all
60 
    run_sim_test subx.s  $all
61 
    run_sim_test tas.s   $all
62 
    run_sim_test xorb.s  $all
63 
    run_sim_test xorw.s  $all
64 
    run_sim_test xorl.s  $all
65 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.