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# Hitachi H8 testcase 'bfld', 'bfst'
# mach(): h8sx
# as(h8300):    --defsym sim_cpu=0
# as(h8300h):   --defsym sim_cpu=1
# as(h8300s):   --defsym sim_cpu=2
# as(h8sx):     --defsym sim_cpu=3
# ld(h8300h):   -m h8300helf
# ld(h8300s):   -m h8300self
# ld(h8sx):     -m h8300sxelf
 
        .include "testutils.inc"
 
        .data
byte_src:       .byte   0xa5
byte_dst:       .byte   0
 
        start
 
.if (sim_cpu == h8sx)
bfld_imm8_ind:
        set_grs_a5a5
        mov     #byte_src, er2
 
        ;; bfld #xx:8, @ers, rd8
        set_ccr_zero
        bfld    #1, @er2, r1l
        test_cc_clear
        test_h_gr8 1 r1l
 
        set_ccr_zero
        bfld    #2, @er2, r1l
        test_cc_clear
        test_h_gr8 0 r1l
 
        set_ccr_zero
        bfld    #7, @er2, r1l
        test_cc_clear
        test_h_gr8 5 r1l
 
        set_ccr_zero
        bfld    #0x10, @er2, r1l
        test_cc_clear
        test_h_gr8 0 r1l
 
        set_ccr_zero
        bfld    #0x20, @er2, r1l
        test_cc_clear
        test_h_gr8 1 r1l
 
        set_ccr_zero
        bfld    #0xf0, @er2, r1l
        test_cc_clear
        test_h_gr8 0xa r1l
 
        test_h_gr32 0xa5a5a5a5 er0
        test_h_gr32 0xa5a5a50a er1
        test_h_gr32 byte_src   er2
        test_h_gr32 0xa5a5a5a5 er3
        test_h_gr32 0xa5a5a5a5 er4
        test_h_gr32 0xa5a5a5a5 er5
        test_h_gr32 0xa5a5a5a5 er6
        test_h_gr32 0xa5a5a5a5 er7
 
bfld_imm8_abs16:
        set_grs_a5a5
 
        ;; bfld #xx:8, @aa:16, rd8
        set_ccr_zero
        bfld    #0x80, @byte_src:16, r1l
        test_cc_clear
        test_h_gr8 1 r1l
 
        set_ccr_zero
        bfld    #0x40, @byte_src:16, r1l
        test_cc_clear
        test_h_gr8 0 r1l
 
        set_ccr_zero
        bfld    #0xe0, @byte_src:16, r1l
        test_cc_clear
        test_h_gr8 0x5 r1l
 
        set_ccr_zero
        bfld    #0x3c, @byte_src:16, r1l
        test_cc_clear
        test_h_gr8 9 r1l
 
        set_ccr_zero
        bfld    #0xfe, @byte_src:16, r1l
        test_cc_clear
        test_h_gr8 0x52 r1l
 
        set_ccr_zero
        bfld    #0, @byte_src:16, r1l
        test_cc_clear
        test_h_gr8 0 r1l
 
        test_h_gr32 0xa5a5a5a5 er0
        test_h_gr32 0xa5a5a500 er1
        test_h_gr32 0xa5a5a5a5 er2
        test_h_gr32 0xa5a5a5a5 er3
        test_h_gr32 0xa5a5a5a5 er4
        test_h_gr32 0xa5a5a5a5 er5
        test_h_gr32 0xa5a5a5a5 er6
        test_h_gr32 0xa5a5a5a5 er7
 
bfst_imm8_ind:
        set_grs_a5a5
        mov     #byte_dst, er2
 
        ;; bfst rd8, #xx:8, @ers
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #1, @er2
;;;     .word   0x7d20
;;;     .word   0xf901
 
        test_cc_clear
        cmp.b   #1, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #2, @er2
;;;     .word   0x7d20
;;;     .word   0xf902
 
        test_cc_clear
        cmp.b   #2, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #7, @er2
;;;     .word   0x7d20
;;;     .word   0xf907
 
        test_cc_clear
        cmp.b   #5, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #0x10, @er2
;;;     .word   0x7d20
;;;     .word   0xf910
 
        test_cc_clear
        cmp.b   #0x10, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #0x20, @er2
;;;     .word   0x7d20
;;;     .word   0xf920
 
        test_cc_clear
        cmp.b   #0x20, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #0xf0, @er2
;;;     .word   0x7d20
;;;     .word   0xf9f0
 
        test_cc_clear
        cmp.b   #0x50, @byte_dst
        bne     fail1:16
 
        test_h_gr32 0xa5a5a5a5 er0
        test_h_gr32 0xa5a5a5a5 er1
        test_h_gr32 byte_dst   er2
        test_h_gr32 0xa5a5a5a5 er3
        test_h_gr32 0xa5a5a5a5 er4
        test_h_gr32 0xa5a5a5a5 er5
        test_h_gr32 0xa5a5a5a5 er6
        test_h_gr32 0xa5a5a5a5 er7
 
bfst_imm8_abs32:
        set_grs_a5a5
 
        ;; bfst #xx:8, @aa:32, rd8
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #0x80, @byte_dst:32
;;;     .word   0x6a38
;;;     .long   byte_dst
;;;     .word   0xf980
 
        test_cc_clear
        cmp.b   #0x80, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #0x40, @byte_dst:32
;;;     .word   0x6a38
;;;     .long   byte_dst
;;;     .word   0xf940
 
        test_cc_clear
        cmp.b   #0x40, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #0xe0, @byte_dst:32
;;;     .word   0x6a38
;;;     .long   byte_dst
;;;     .word   0xf9e0
 
        test_cc_clear
        cmp.b   #0xa0, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #0x3c, @byte_dst:32
;;;     .word   0x6a38
;;;     .long   byte_dst
;;;     .word   0xf93c
 
        test_cc_clear
        cmp.b   #0x14, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #0xfe, @byte_dst:32
;;;     .word   0x6a38
;;;     .long   byte_dst
;;;     .word   0xf9fe
 
        test_cc_clear
        cmp.b   #0x4a, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #0, @byte_dst:32
;;;     .word   0x6a38
;;;     .long   byte_dst
;;;     .word   0xf900
 
        test_cc_clear
        cmp.b   #0x0, @byte_dst
        bne     fail1:16
 
        mov.b   #0, @byte_dst
        set_ccr_zero
        bfst    r1l, #0x38, @byte_dst:32
;;;     .word   0x6a38
;;;     .long   byte_dst
;;;     .word   0xf938
 
        test_cc_clear
        cmp.b   #0x28, @byte_dst
        bne     fail1:16
 
        ;;
        ;; Now let's do one in which the bits in the destination
        ;; are appropriately combined with the bits in the source.
        ;;
 
        mov.b   #0xc3, @byte_dst
        set_ccr_zero
        bfst    r1l, #0x3c, @byte_dst:32
;;;     .word   0x6a38
;;;     .long   byte_dst
;;;     .word   0xf93c
 
        test_cc_clear
        cmp.b   #0xd7, @byte_dst
        bne     fail1:16
 
        test_grs_a5a5
 
.endif
        pass
 
        exit 0
 
fail1:  fail
 

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [bfld.s] - Blame information for rev 280

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Hitachi H8 testcase 'bfld', 'bfst'`
2			`# mach(): h8sx`
3			`# as(h8300): --defsym sim_cpu=0`
4			`# as(h8300h): --defsym sim_cpu=1`
5			`# as(h8300s): --defsym sim_cpu=2`
6			`# as(h8sx): --defsym sim_cpu=3`
7			`# ld(h8300h): -m h8300helf`
8			`# ld(h8300s): -m h8300self`
9			`# ld(h8sx): -m h8300sxelf`
10
11			`.include "testutils.inc"`
12
13			`.data`
14			`byte_src: .byte 0xa5`
15			`byte_dst: .byte 0`
16
17			`start`
18
19			`.if (sim_cpu == h8sx)`
20			`bfld_imm8_ind:`
21			`set_grs_a5a5`
22			`mov #byte_src, er2`
23
24			`;; bfld #xx:8, @ers, rd8`
25			`set_ccr_zero`
26			`bfld #1, @er2, r1l`
27			`test_cc_clear`
28			`test_h_gr8 1 r1l`
29
30			`set_ccr_zero`
31			`bfld #2, @er2, r1l`
32			`test_cc_clear`
33			`test_h_gr8 0 r1l`
34
35			`set_ccr_zero`
36			`bfld #7, @er2, r1l`
37			`test_cc_clear`
38			`test_h_gr8 5 r1l`
39
40			`set_ccr_zero`
41			`bfld #0x10, @er2, r1l`
42			`test_cc_clear`
43			`test_h_gr8 0 r1l`
44
45			`set_ccr_zero`
46			`bfld #0x20, @er2, r1l`
47			`test_cc_clear`
48			`test_h_gr8 1 r1l`
49
50			`set_ccr_zero`
51			`bfld #0xf0, @er2, r1l`
52			`test_cc_clear`
53			`test_h_gr8 0xa r1l`
54
55			`test_h_gr32 0xa5a5a5a5 er0`
56			`test_h_gr32 0xa5a5a50a er1`
57			`test_h_gr32 byte_src er2`
58			`test_h_gr32 0xa5a5a5a5 er3`
59			`test_h_gr32 0xa5a5a5a5 er4`
60			`test_h_gr32 0xa5a5a5a5 er5`
61			`test_h_gr32 0xa5a5a5a5 er6`
62			`test_h_gr32 0xa5a5a5a5 er7`
63
64			`bfld_imm8_abs16:`
65			`set_grs_a5a5`
66
67			`;; bfld #xx:8, @aa:16, rd8`
68			`set_ccr_zero`
69			`bfld #0x80, @byte_src:16, r1l`
70			`test_cc_clear`
71			`test_h_gr8 1 r1l`
72
73			`set_ccr_zero`
74			`bfld #0x40, @byte_src:16, r1l`
75			`test_cc_clear`
76			`test_h_gr8 0 r1l`
77
78			`set_ccr_zero`
79			`bfld #0xe0, @byte_src:16, r1l`
80			`test_cc_clear`
81			`test_h_gr8 0x5 r1l`
82
83			`set_ccr_zero`
84			`bfld #0x3c, @byte_src:16, r1l`
85			`test_cc_clear`
86			`test_h_gr8 9 r1l`
87
88			`set_ccr_zero`
89			`bfld #0xfe, @byte_src:16, r1l`
90			`test_cc_clear`
91			`test_h_gr8 0x52 r1l`
92
93			`set_ccr_zero`
94			`bfld #0, @byte_src:16, r1l`
95			`test_cc_clear`
96			`test_h_gr8 0 r1l`
97
98			`test_h_gr32 0xa5a5a5a5 er0`
99			`test_h_gr32 0xa5a5a500 er1`
100			`test_h_gr32 0xa5a5a5a5 er2`
101			`test_h_gr32 0xa5a5a5a5 er3`
102			`test_h_gr32 0xa5a5a5a5 er4`
103			`test_h_gr32 0xa5a5a5a5 er5`
104			`test_h_gr32 0xa5a5a5a5 er6`
105			`test_h_gr32 0xa5a5a5a5 er7`
106
107			`bfst_imm8_ind:`
108			`set_grs_a5a5`
109			`mov #byte_dst, er2`
110
111			`;; bfst rd8, #xx:8, @ers`
112			`mov.b #0, @byte_dst`
113			`set_ccr_zero`
114			`bfst r1l, #1, @er2`
115			`;;; .word 0x7d20`
116			`;;; .word 0xf901`
117
118			`test_cc_clear`
119			`cmp.b #1, @byte_dst`
120			`bne fail1:16`
121
122			`mov.b #0, @byte_dst`
123			`set_ccr_zero`
124			`bfst r1l, #2, @er2`
125			`;;; .word 0x7d20`
126			`;;; .word 0xf902`
127
128			`test_cc_clear`
129			`cmp.b #2, @byte_dst`
130			`bne fail1:16`
131
132			`mov.b #0, @byte_dst`
133			`set_ccr_zero`
134			`bfst r1l, #7, @er2`
135			`;;; .word 0x7d20`
136			`;;; .word 0xf907`
137
138			`test_cc_clear`
139			`cmp.b #5, @byte_dst`
140			`bne fail1:16`
141
142			`mov.b #0, @byte_dst`
143			`set_ccr_zero`
144			`bfst r1l, #0x10, @er2`
145			`;;; .word 0x7d20`
146			`;;; .word 0xf910`
147
148			`test_cc_clear`
149			`cmp.b #0x10, @byte_dst`
150			`bne fail1:16`
151
152			`mov.b #0, @byte_dst`
153			`set_ccr_zero`
154			`bfst r1l, #0x20, @er2`
155			`;;; .word 0x7d20`
156			`;;; .word 0xf920`
157
158			`test_cc_clear`
159			`cmp.b #0x20, @byte_dst`
160			`bne fail1:16`
161
162			`mov.b #0, @byte_dst`
163			`set_ccr_zero`
164			`bfst r1l, #0xf0, @er2`
165			`;;; .word 0x7d20`
166			`;;; .word 0xf9f0`
167
168			`test_cc_clear`
169			`cmp.b #0x50, @byte_dst`
170			`bne fail1:16`
171
172			`test_h_gr32 0xa5a5a5a5 er0`
173			`test_h_gr32 0xa5a5a5a5 er1`
174			`test_h_gr32 byte_dst er2`
175			`test_h_gr32 0xa5a5a5a5 er3`
176			`test_h_gr32 0xa5a5a5a5 er4`
177			`test_h_gr32 0xa5a5a5a5 er5`
178			`test_h_gr32 0xa5a5a5a5 er6`
179			`test_h_gr32 0xa5a5a5a5 er7`
180
181			`bfst_imm8_abs32:`
182			`set_grs_a5a5`
183
184			`;; bfst #xx:8, @aa:32, rd8`
185			`mov.b #0, @byte_dst`
186			`set_ccr_zero`
187			`bfst r1l, #0x80, @byte_dst:32`
188			`;;; .word 0x6a38`
189			`;;; .long byte_dst`
190			`;;; .word 0xf980`
191
192			`test_cc_clear`
193			`cmp.b #0x80, @byte_dst`
194			`bne fail1:16`
195
196			`mov.b #0, @byte_dst`
197			`set_ccr_zero`
198			`bfst r1l, #0x40, @byte_dst:32`
199			`;;; .word 0x6a38`
200			`;;; .long byte_dst`
201			`;;; .word 0xf940`
202
203			`test_cc_clear`
204			`cmp.b #0x40, @byte_dst`
205			`bne fail1:16`
206
207			`mov.b #0, @byte_dst`
208			`set_ccr_zero`
209			`bfst r1l, #0xe0, @byte_dst:32`
210			`;;; .word 0x6a38`
211			`;;; .long byte_dst`
212			`;;; .word 0xf9e0`
213
214			`test_cc_clear`
215			`cmp.b #0xa0, @byte_dst`
216			`bne fail1:16`
217
218			`mov.b #0, @byte_dst`
219			`set_ccr_zero`
220			`bfst r1l, #0x3c, @byte_dst:32`
221			`;;; .word 0x6a38`
222			`;;; .long byte_dst`
223			`;;; .word 0xf93c`
224
225			`test_cc_clear`
226			`cmp.b #0x14, @byte_dst`
227			`bne fail1:16`
228
229			`mov.b #0, @byte_dst`
230			`set_ccr_zero`
231			`bfst r1l, #0xfe, @byte_dst:32`
232			`;;; .word 0x6a38`
233			`;;; .long byte_dst`
234			`;;; .word 0xf9fe`
235
236			`test_cc_clear`
237			`cmp.b #0x4a, @byte_dst`
238			`bne fail1:16`
239
240			`mov.b #0, @byte_dst`
241			`set_ccr_zero`
242			`bfst r1l, #0, @byte_dst:32`
243			`;;; .word 0x6a38`
244			`;;; .long byte_dst`
245			`;;; .word 0xf900`
246
247			`test_cc_clear`
248			`cmp.b #0x0, @byte_dst`
249			`bne fail1:16`
250
251			`mov.b #0, @byte_dst`
252			`set_ccr_zero`
253			`bfst r1l, #0x38, @byte_dst:32`
254			`;;; .word 0x6a38`
255			`;;; .long byte_dst`
256			`;;; .word 0xf938`
257
258			`test_cc_clear`
259			`cmp.b #0x28, @byte_dst`
260			`bne fail1:16`
261
262			`;;`
263			`;; Now let's do one in which the bits in the destination`
264			`;; are appropriately combined with the bits in the source.`
265			`;;`
266
267			`mov.b #0xc3, @byte_dst`
268			`set_ccr_zero`
269			`bfst r1l, #0x3c, @byte_dst:32`
270			`;;; .word 0x6a38`
271			`;;; .long byte_dst`
272			`;;; .word 0xf93c`
273
274			`test_cc_clear`
275			`cmp.b #0xd7, @byte_dst`
276			`bne fail1:16`
277
278			`test_grs_a5a5`
279
280			`.endif`
281			`pass`
282
283			`exit 0`
284
285			`fail1: fail`
286