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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [bra.s] - Blame information for rev 280

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Line No. Rev Author Line
1 24 jeremybenn 
# Hitachi H8 testcase 'bra'
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# mach(): all
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# as(h8300):    --defsym sim_cpu=0
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# as(h8300h):   --defsym sim_cpu=1
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# as(h8300s):   --defsym sim_cpu=2
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# as(h8sx):     --defsym sim_cpu=3
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# ld(h8300h):   -m h8300helf
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# ld(h8300s):   -m h8300self
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# ld(h8sx):     -m h8300sxelf
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        .include "testutils.inc"
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        start
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.if (sim_cpu == h8sx)
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        .data
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        .align 4
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disp8:  .long   tgt_reg8
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disp16: .long   tgt_reg16
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disp32: .long   tgt_reg32
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dslot:  .byte   0
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        .text
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.endif
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bra_8:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        ;;  bra dd:8            ; 8-bit displacement
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        bra tgt_8:8
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;;;     .word   0x40xx          ; where "xx" is tgt_8 - '.'.
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        fail
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tgt_8:
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        test_cc_clear
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        test_gr_a5a5 0           ; Make sure other general regs not disturbed
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        test_gr_a5a5 1
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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.if (sim_cpu)                   ; not available in h8/300 mode
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bra_16:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        ;;  bra dd:16           ; 16-bit displacement
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        bra tgt_24:16   ; NOTE: hard-coded to avoid relaxing.
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;;;     .word 0x5800
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;;;     .word tgt_24 - .
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        fail
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tgt_24:
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        test_cc_clear
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        test_gr_a5a5 0           ; Make sure other general regs not disturbed
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        test_gr_a5a5 1
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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.endif
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.if     (sim_cpu == h8sx)
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bra_reg8:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        ;;  bra rn.b            ; 8-bit register indirect
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        sub.l   #src8, @disp8
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        mov.l   @disp8, er5
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        bra     r5l.b
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;;;     .word   0x5955
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src8:   fail
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tgt_reg8:
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        test_cc_clear
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        test_gr_a5a5 0           ; Make sure other general regs not disturbed
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        test_gr_a5a5 1
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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;;;     test_h_gr32 tgt_reg8 er5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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bra_reg16:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        ;;  bra rn.w            ; 16-bit register indirect
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        sub.l   #src16, @disp16
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        mov.l   @disp16, er5
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        bra     r5.w
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;;;     .word   0x5956
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src16:  fail
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tgt_reg16:
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        test_cc_clear
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        test_gr_a5a5 0           ; Make sure other general regs not disturbed
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        test_gr_a5a5 1
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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;;;     test_h_gr32 tgt_reg16 er5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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bra_reg32:
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        set_grs_a5a5            ; Fill all general regs with a fixed pattern
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        set_ccr_zero
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        ;;  bra ern             ; 32-bit register indirect
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        sub.l   #src32, @disp32
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        mov.l   @disp32, er5
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        bra     er5.l
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;;;     .word   0x5957
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src32:  fail
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tgt_reg32:
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        test_cc_clear
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        test_gr_a5a5 0           ; Make sure other general regs not disturbed
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        test_gr_a5a5 1
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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;;;     test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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bra_s:  set_grs_a5a5
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        set_ccr_zero
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        bra/s   tgt_post_delay
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;;;     .word   0x4017
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        ;; The following instruction is in the delay slot, and should execute.
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        mov.b   #1, @dslot
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        ;; After this, the next instructions should not execute.
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        fail
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tgt_post_delay:
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        test_cc_clear
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        cmp.b   #0, @dslot       ; Should be non-zero if delay slot executed.
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        bne     dslot_ok
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        fail
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dslot_ok:
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        test_gr_a5a5 0           ; Make sure all general regs not disturbed
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        test_gr_a5a5 1
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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.endif
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        pass
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        exit 0
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