URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [ldc.s] - Blame information for rev 407

Go to most recent revision | Details | Compare with Previous | View Log


# Hitachi H8 testcase 'ldc'
# mach(): all
# as(h8300):    --defsym sim_cpu=0
# as(h8300h):   --defsym sim_cpu=1
# as(h8300s):   --defsym sim_cpu=2
# as(h8sx):     --defsym sim_cpu=3
# ld(h8300h):   -m h8300helf
# ld(h8300s):   -m h8300self
# ld(h8sx):     -m h8300sxelf
 
        .include "testutils.inc"
        .data
byte_pre:
        .byte   0
byte_src:
        .byte   0xff
byte_post:
        .byte   0
 
        start
 
ldc_imm8_ccr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     #0xff, ccr      ; set all ccr flags high, immediate operand
        bcs     .L1             ; carry flag set?
        fail
.L1:    bvs     .L2             ; overflow flag set?
        fail
.L2:    beq     .L3             ; zero flag set?
        fail
.L3:    bmi     .L4             ; neg flag set?
        fail
.L4:
        ldc     #0, ccr          ; set all ccr flags low, immediate operand
        bcc     .L5             ; carry flag clear?
        fail
.L5:    bvc     .L6             ; overflow flag clear?
        fail
.L6:    bne     .L7             ; zero flag clear?
        fail
.L7:    bpl     .L8             ; neg flag clear?
        fail
.L8:
        test_cc_clear
        test_grs_a5a5
 
ldc_reg8_ccr:
        set_grs_a5a5
        set_ccr_zero
 
        mov     #0xff, r0h
        ldc     r0h, ccr        ; set all ccr flags high, reg operand
        bcs     .L11            ; carry flag set?
        fail
.L11:   bvs     .L12            ; overflow flag set?
        fail
.L12:   beq     .L13            ; zero flag set?
        fail
.L13:   bmi     .L14            ; neg flag set?
        fail
.L14:
        mov     #0, r0h
        ldc     r0h, ccr        ; set all ccr flags low, reg operand
        bcc     .L15            ; carry flag clear?
        fail
.L15:   bvc     .L16            ; overflow flag clear?
        fail
.L16:   bne     .L17            ; zero flag clear?
        fail
.L17:   bpl     .L18            ; neg flag clear?
        fail
.L18:
        test_cc_clear
        test_h_gr16  0x00a5 r0  ; Register 0 modified by test procedure.
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.if (sim_cpu == h8300s || sim_cpu == h8sx)      ; Earlier versions, no exr
ldc_imm8_exr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     #0, exr
        ldc     #0x87, exr      ; set exr to 0x87
 
        stc     exr, r0l        ; retrieve and check exr value
        cmp.b   #0x87, r0l
        beq     .L19
        fail
.L19:
        test_h_gr16  0xa587 r0  ; Register 0 modified by test procedure.
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_reg8_exr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     #0, exr
        mov     #0x87, r0h
        ldc     r0h, exr        ; set exr to 0x87
 
        stc     exr, r0l        ; retrieve and check exr value
        cmp.b   #0x87, r0l
        beq     .L21
        fail
.L21:
        test_h_gr16  0x8787 r0  ; Register 0 modified by test procedure.
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_abs16_ccr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     @byte_src:16, ccr       ; abs16 src
        stc     ccr, r0l        ; copy into general reg
 
        test_h_gr32 0xa5a5a5ff er0      ; ff in r0l, a5 elsewhere.
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_abs16_exr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     #0, exr
        ldc     @byte_src:16, exr       ; abs16 src
        stc     exr, r0l        ; copy into general reg
 
        test_h_gr32 0xa5a5a587 er0      ; 87 in r0l, a5 elsewhere.
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_abs32_ccr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     @byte_src:32, ccr       ; abs32 src
        stc     ccr, r0l        ; copy into general reg
 
        test_h_gr32 0xa5a5a5ff er0      ; ff in r0l, a5 elsewhere.
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_abs32_exr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     #0, exr
        ldc     @byte_src:32, exr       ; abs32 src
        stc     exr, r0l        ; copy into general reg
 
        test_h_gr32 0xa5a5a587 er0      ; 87 in r0l, a5 elsewhere.
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_disp16_ccr:
        set_grs_a5a5
        set_ccr_zero
 
        mov     #byte_pre, er1
        ldc     @(1:16, er1), ccr       ; disp16 src
        stc     ccr, r0l        ; copy into general reg
 
        test_h_gr32 0xa5a5a5ff er0      ; ff in r0l, a5 elsewhere.
        test_h_gr32 byte_pre, er1       ; er1 still contains address
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_disp16_exr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     #0, exr
        mov     #byte_post, er1
        ldc     @(-1:16, er1), exr      ; disp16 src
        stc     exr, r0l        ; copy into general reg
 
        test_h_gr32 0xa5a5a587 er0      ; 87 in r0l, a5 elsewhere.
        test_h_gr32 byte_post, er1      ; er1 still contains address
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_disp32_ccr:
        set_grs_a5a5
        set_ccr_zero
 
        mov     #byte_pre, er1
        ldc     @(1:32, er1), ccr       ; disp32 src
        stc     ccr, r0l        ; copy into general reg
 
        test_h_gr32 0xa5a5a5ff er0      ; ff in r0l, a5 elsewhere.
        test_h_gr32 byte_pre, er1       ; er1 still contains address
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_disp32_exr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     #0, exr
        mov     #byte_post, er1
        ldc     @(-1:32, er1), exr      ; disp16 src
        stc     exr, r0l        ; copy into general reg
 
        test_h_gr32 0xa5a5a587 er0      ; 87 in r0l, a5 elsewhere.
        test_h_gr32 byte_post, er1      ; er1 still contains address
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_postinc_ccr:
        set_grs_a5a5
        set_ccr_zero
 
        mov     #byte_src, er1
        ldc     @er1+, ccr      ; postinc src
        stc     ccr, r0l        ; copy into general reg
 
        test_h_gr32  0xa5a5a5ff er0     ; ff in r0l, a5 elsewhere.
        test_h_gr32  byte_src+2, er1    ; er1 still contains address
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_postinc_exr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     #0, exr
        mov     #byte_src, er1
        ldc     @er1+, exr      ; postinc src
        stc     exr, r0l        ; copy into general reg
 
        test_h_gr32  0xa5a5a587 er0     ; 87 in r0l, a5 elsewhere.
        test_h_gr32  byte_src+2, er1    ; er1 still contains address
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_ind_ccr:
        set_grs_a5a5
        set_ccr_zero
 
        mov     #byte_src, er1
        ldc     @er1, ccr       ; postinc src
        stc     ccr, r0l        ; copy into general reg
 
        test_h_gr32 0xa5a5a5ff er0      ; ff in r0l, a5 elsewhere.
        test_h_gr32 byte_src, er1       ; er1 still contains address
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_ind_exr:
        set_grs_a5a5
        set_ccr_zero
 
        ldc     #0, exr
        mov     #byte_src, er1
        ldc     @er1, exr       ; postinc src
        stc     exr, r0l        ; copy into general reg
 
        test_h_gr32 0xa5a5a587 er0      ; 87 in r0l, a5 elsewhere.
        test_h_gr32 byte_src, er1       ; er1 still contains address
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.endif
 
.if (sim_cpu == h8sx)           ; New vbr and sbr registers for h8sx
ldc_reg_sbr:
        set_grs_a5a5
        set_ccr_zero
 
        mov     #0xaaaaaaaa, er0
        ldc     er0, sbr        ; set sbr to 0xaaaaaaaa
        stc     sbr, er1        ; retreive and check sbr value
 
        test_h_gr32 0xaaaaaaaa er1
        test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
ldc_reg_vbr:
        set_grs_a5a5
        set_ccr_zero
 
        mov     #0xaaaaaaaa, er0
        ldc     er0, vbr        ; set sbr to 0xaaaaaaaa
        stc     vbr, er1        ; retreive and check sbr value
 
        test_h_gr32 0xaaaaaaaa er1
        test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.endif
        pass
 
        exit 0

Browse

Tools

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [ldc.s] - Blame information for rev 407

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Hitachi H8 testcase 'ldc'`
2			`# mach(): all`
3			`# as(h8300): --defsym sim_cpu=0`
4			`# as(h8300h): --defsym sim_cpu=1`
5			`# as(h8300s): --defsym sim_cpu=2`
6			`# as(h8sx): --defsym sim_cpu=3`
7			`# ld(h8300h): -m h8300helf`
8			`# ld(h8300s): -m h8300self`
9			`# ld(h8sx): -m h8300sxelf`
10
11			`.include "testutils.inc"`
12			`.data`
13			`byte_pre:`
14			`.byte 0`
15			`byte_src:`
16			`.byte 0xff`
17			`byte_post:`
18			`.byte 0`
19
20			`start`
21
22			`ldc_imm8_ccr:`
23			`set_grs_a5a5`
24			`set_ccr_zero`
25
26			`ldc #0xff, ccr ; set all ccr flags high, immediate operand`
27			`bcs .L1 ; carry flag set?`
28			`fail`
29			`.L1: bvs .L2 ; overflow flag set?`
30			`fail`
31			`.L2: beq .L3 ; zero flag set?`
32			`fail`
33			`.L3: bmi .L4 ; neg flag set?`
34			`fail`
35			`.L4:`
36			`ldc #0, ccr ; set all ccr flags low, immediate operand`
37			`bcc .L5 ; carry flag clear?`
38			`fail`
39			`.L5: bvc .L6 ; overflow flag clear?`
40			`fail`
41			`.L6: bne .L7 ; zero flag clear?`
42			`fail`
43			`.L7: bpl .L8 ; neg flag clear?`
44			`fail`
45			`.L8:`
46			`test_cc_clear`
47			`test_grs_a5a5`
48
49			`ldc_reg8_ccr:`
50			`set_grs_a5a5`
51			`set_ccr_zero`
52
53			`mov #0xff, r0h`
54			`ldc r0h, ccr ; set all ccr flags high, reg operand`
55			`bcs .L11 ; carry flag set?`
56			`fail`
57			`.L11: bvs .L12 ; overflow flag set?`
58			`fail`
59			`.L12: beq .L13 ; zero flag set?`
60			`fail`
61			`.L13: bmi .L14 ; neg flag set?`
62			`fail`
63			`.L14:`
64			`mov #0, r0h`
65			`ldc r0h, ccr ; set all ccr flags low, reg operand`
66			`bcc .L15 ; carry flag clear?`
67			`fail`
68			`.L15: bvc .L16 ; overflow flag clear?`
69			`fail`
70			`.L16: bne .L17 ; zero flag clear?`
71			`fail`
72			`.L17: bpl .L18 ; neg flag clear?`
73			`fail`
74			`.L18:`
75			`test_cc_clear`
76			`test_h_gr16 0x00a5 r0 ; Register 0 modified by test procedure.`
77			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
78			`test_gr_a5a5 2`
79			`test_gr_a5a5 3`
80			`test_gr_a5a5 4`
81			`test_gr_a5a5 5`
82			`test_gr_a5a5 6`
83			`test_gr_a5a5 7`
84
85			`.if (sim_cpu == h8300s \|\| sim_cpu == h8sx) ; Earlier versions, no exr`
86			`ldc_imm8_exr:`
87			`set_grs_a5a5`
88			`set_ccr_zero`
89
90			`ldc #0, exr`
91			`ldc #0x87, exr ; set exr to 0x87`
92
93			`stc exr, r0l ; retrieve and check exr value`
94			`cmp.b #0x87, r0l`
95			`beq .L19`
96			`fail`
97			`.L19:`
98			`test_h_gr16 0xa587 r0 ; Register 0 modified by test procedure.`
99			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
100			`test_gr_a5a5 2`
101			`test_gr_a5a5 3`
102			`test_gr_a5a5 4`
103			`test_gr_a5a5 5`
104			`test_gr_a5a5 6`
105			`test_gr_a5a5 7`
106
107			`ldc_reg8_exr:`
108			`set_grs_a5a5`
109			`set_ccr_zero`
110
111			`ldc #0, exr`
112			`mov #0x87, r0h`
113			`ldc r0h, exr ; set exr to 0x87`
114
115			`stc exr, r0l ; retrieve and check exr value`
116			`cmp.b #0x87, r0l`
117			`beq .L21`
118			`fail`
119			`.L21:`
120			`test_h_gr16 0x8787 r0 ; Register 0 modified by test procedure.`
121			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
122			`test_gr_a5a5 2`
123			`test_gr_a5a5 3`
124			`test_gr_a5a5 4`
125			`test_gr_a5a5 5`
126			`test_gr_a5a5 6`
127			`test_gr_a5a5 7`
128
129			`ldc_abs16_ccr:`
130			`set_grs_a5a5`
131			`set_ccr_zero`
132
133			`ldc @byte_src:16, ccr ; abs16 src`
134			`stc ccr, r0l ; copy into general reg`
135
136			`test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.`
137			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
138			`test_gr_a5a5 2`
139			`test_gr_a5a5 3`
140			`test_gr_a5a5 4`
141			`test_gr_a5a5 5`
142			`test_gr_a5a5 6`
143			`test_gr_a5a5 7`
144
145			`ldc_abs16_exr:`
146			`set_grs_a5a5`
147			`set_ccr_zero`
148
149			`ldc #0, exr`
150			`ldc @byte_src:16, exr ; abs16 src`
151			`stc exr, r0l ; copy into general reg`
152
153			`test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.`
154			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
155			`test_gr_a5a5 2`
156			`test_gr_a5a5 3`
157			`test_gr_a5a5 4`
158			`test_gr_a5a5 5`
159			`test_gr_a5a5 6`
160			`test_gr_a5a5 7`
161
162			`ldc_abs32_ccr:`
163			`set_grs_a5a5`
164			`set_ccr_zero`
165
166			`ldc @byte_src:32, ccr ; abs32 src`
167			`stc ccr, r0l ; copy into general reg`
168
169			`test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.`
170			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
171			`test_gr_a5a5 2`
172			`test_gr_a5a5 3`
173			`test_gr_a5a5 4`
174			`test_gr_a5a5 5`
175			`test_gr_a5a5 6`
176			`test_gr_a5a5 7`
177
178			`ldc_abs32_exr:`
179			`set_grs_a5a5`
180			`set_ccr_zero`
181
182			`ldc #0, exr`
183			`ldc @byte_src:32, exr ; abs32 src`
184			`stc exr, r0l ; copy into general reg`
185
186			`test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.`
187			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
188			`test_gr_a5a5 2`
189			`test_gr_a5a5 3`
190			`test_gr_a5a5 4`
191			`test_gr_a5a5 5`
192			`test_gr_a5a5 6`
193			`test_gr_a5a5 7`
194
195			`ldc_disp16_ccr:`
196			`set_grs_a5a5`
197			`set_ccr_zero`
198
199			`mov #byte_pre, er1`
200			`ldc @(1:16, er1), ccr ; disp16 src`
201			`stc ccr, r0l ; copy into general reg`
202
203			`test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.`
204			`test_h_gr32 byte_pre, er1 ; er1 still contains address`
205			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
206			`test_gr_a5a5 3`
207			`test_gr_a5a5 4`
208			`test_gr_a5a5 5`
209			`test_gr_a5a5 6`
210			`test_gr_a5a5 7`
211
212			`ldc_disp16_exr:`
213			`set_grs_a5a5`
214			`set_ccr_zero`
215
216			`ldc #0, exr`
217			`mov #byte_post, er1`
218			`ldc @(-1:16, er1), exr ; disp16 src`
219			`stc exr, r0l ; copy into general reg`
220
221			`test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.`
222			`test_h_gr32 byte_post, er1 ; er1 still contains address`
223			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
224			`test_gr_a5a5 3`
225			`test_gr_a5a5 4`
226			`test_gr_a5a5 5`
227			`test_gr_a5a5 6`
228			`test_gr_a5a5 7`
229
230			`ldc_disp32_ccr:`
231			`set_grs_a5a5`
232			`set_ccr_zero`
233
234			`mov #byte_pre, er1`
235			`ldc @(1:32, er1), ccr ; disp32 src`
236			`stc ccr, r0l ; copy into general reg`
237
238			`test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.`
239			`test_h_gr32 byte_pre, er1 ; er1 still contains address`
240			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
241			`test_gr_a5a5 3`
242			`test_gr_a5a5 4`
243			`test_gr_a5a5 5`
244			`test_gr_a5a5 6`
245			`test_gr_a5a5 7`
246
247			`ldc_disp32_exr:`
248			`set_grs_a5a5`
249			`set_ccr_zero`
250
251			`ldc #0, exr`
252			`mov #byte_post, er1`
253			`ldc @(-1:32, er1), exr ; disp16 src`
254			`stc exr, r0l ; copy into general reg`
255
256			`test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.`
257			`test_h_gr32 byte_post, er1 ; er1 still contains address`
258			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
259			`test_gr_a5a5 3`
260			`test_gr_a5a5 4`
261			`test_gr_a5a5 5`
262			`test_gr_a5a5 6`
263			`test_gr_a5a5 7`
264
265			`ldc_postinc_ccr:`
266			`set_grs_a5a5`
267			`set_ccr_zero`
268
269			`mov #byte_src, er1`
270			`ldc @er1+, ccr ; postinc src`
271			`stc ccr, r0l ; copy into general reg`
272
273			`test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.`
274			`test_h_gr32 byte_src+2, er1 ; er1 still contains address`
275			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
276			`test_gr_a5a5 3`
277			`test_gr_a5a5 4`
278			`test_gr_a5a5 5`
279			`test_gr_a5a5 6`
280			`test_gr_a5a5 7`
281
282			`ldc_postinc_exr:`
283			`set_grs_a5a5`
284			`set_ccr_zero`
285
286			`ldc #0, exr`
287			`mov #byte_src, er1`
288			`ldc @er1+, exr ; postinc src`
289			`stc exr, r0l ; copy into general reg`
290
291			`test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.`
292			`test_h_gr32 byte_src+2, er1 ; er1 still contains address`
293			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
294			`test_gr_a5a5 3`
295			`test_gr_a5a5 4`
296			`test_gr_a5a5 5`
297			`test_gr_a5a5 6`
298			`test_gr_a5a5 7`
299
300			`ldc_ind_ccr:`
301			`set_grs_a5a5`
302			`set_ccr_zero`
303
304			`mov #byte_src, er1`
305			`ldc @er1, ccr ; postinc src`
306			`stc ccr, r0l ; copy into general reg`
307
308			`test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.`
309			`test_h_gr32 byte_src, er1 ; er1 still contains address`
310			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
311			`test_gr_a5a5 3`
312			`test_gr_a5a5 4`
313			`test_gr_a5a5 5`
314			`test_gr_a5a5 6`
315			`test_gr_a5a5 7`
316
317			`ldc_ind_exr:`
318			`set_grs_a5a5`
319			`set_ccr_zero`
320
321			`ldc #0, exr`
322			`mov #byte_src, er1`
323			`ldc @er1, exr ; postinc src`
324			`stc exr, r0l ; copy into general reg`
325
326			`test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.`
327			`test_h_gr32 byte_src, er1 ; er1 still contains address`
328			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
329			`test_gr_a5a5 3`
330			`test_gr_a5a5 4`
331			`test_gr_a5a5 5`
332			`test_gr_a5a5 6`
333			`test_gr_a5a5 7`
334
335			`.endif`
336
337			`.if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx`
338			`ldc_reg_sbr:`
339			`set_grs_a5a5`
340			`set_ccr_zero`
341
342			`mov #0xaaaaaaaa, er0`
343			`ldc er0, sbr ; set sbr to 0xaaaaaaaa`
344			`stc sbr, er1 ; retreive and check sbr value`
345
346			`test_h_gr32 0xaaaaaaaa er1`
347			`test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.`
348			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
349			`test_gr_a5a5 3`
350			`test_gr_a5a5 4`
351			`test_gr_a5a5 5`
352			`test_gr_a5a5 6`
353			`test_gr_a5a5 7`
354
355			`ldc_reg_vbr:`
356			`set_grs_a5a5`
357			`set_ccr_zero`
358
359			`mov #0xaaaaaaaa, er0`
360			`ldc er0, vbr ; set sbr to 0xaaaaaaaa`
361			`stc vbr, er1 ; retreive and check sbr value`
362
363			`test_h_gr32 0xaaaaaaaa er1`
364			`test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.`
365			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
366			`test_gr_a5a5 3`
367			`test_gr_a5a5 4`
368			`test_gr_a5a5 5`
369			`test_gr_a5a5 6`
370			`test_gr_a5a5 7`
371
372			`.endif`
373			`pass`
374
375			`exit 0`