URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [movmd.s] - Blame information for rev 280

Go to most recent revision | Details | Compare with Previous | View Log


# Hitachi H8 testcase 'movmd'
# mach(): h8sx
# as(h8300):    --defsym sim_cpu=0
# as(h8300h):   --defsym sim_cpu=1
# as(h8300s):   --defsym sim_cpu=2
# as(h8sx):     --defsym sim_cpu=3
# ld(h8300h):   -m h8300helf
# ld(h8300s):   -m h8300self
# ld(h8sx):     -m h8300sxelf
 
        .include "testutils.inc"
 
        .data
byte_src:
        .byte   1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
byte_dst:
        .byte   0, 0, 0, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0
 
        .align 2
word_src:
        .word   1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
word_dst:
        .word   0, 0, 0, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0
 
        .align 4
long_src:
        .long   1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
long_dst:
        .long   0, 0, 0, 0, 0, 0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0
 
        start
.if (sim_cpu == h8sx)
movmd_b:#
        # Byte block transfer
        #
        set_grs_a5a5
 
        mov     #byte_src, er5
        mov     #byte_dst, er6
        mov     #10, r4
        set_ccr_zero
        ;; movmd.b
        movmd.b
;;;     .word   0x7b94
 
        test_cc_clear
        test_gr_a5a5 0
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_h_gr32  0xa5a50000  er4
        test_h_gr32  byte_src+10 er5
        test_h_gr32  byte_dst+10 er6
        test_gr_a5a5 7
 
        #
        # Now make sure exactly 10 bytes were transferred.
        memcmp  byte_src byte_dst 10
        cmp.b   #0, @byte_dst+10
        beq     .L0
        fail
.L0:
 
movmd_w:#
        # Word block transfer
        #
        set_grs_a5a5
 
        mov     #word_src, er5
        mov     #word_dst, er6
        mov     #10, r4
        set_ccr_zero
        ;; movmd.w
        movmd.w
;;;     .word   0x7ba4
 
        test_cc_clear
        test_gr_a5a5 0
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_h_gr32  0xa5a50000  er4
        test_h_gr32  word_src+20 er5
        test_h_gr32  word_dst+20 er6
        test_gr_a5a5 7
 
        #
        # Now make sure exactly 20 bytes were transferred.
        memcmp  word_src word_dst 20
        cmp.w   #0, @word_dst+20
        beq     .L1
        fail
.L1:
 
movmd_l:#
        # Long block transfer
        #
        set_grs_a5a5
 
        mov     #long_src, er5
        mov     #long_dst, er6
        mov     #10, r4
        set_ccr_zero
        ;; movmd.b
        movmd.l
;;;     .word   0x7bb4
 
        test_cc_clear
        test_gr_a5a5 0
        test_gr_a5a5 1
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_h_gr32  0xa5a50000  er4
        test_h_gr32  long_src+40 er5
        test_h_gr32  long_dst+40 er6
        test_gr_a5a5 7
 
        #
        # Now make sure exactly 40 bytes were transferred.
        memcmp  long_src long_dst 40
        cmp.l   #0, @long_dst+40
        beq     .L2
        fail
.L2:
 
.endif
        pass
 
        exit 0

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Hitachi H8 testcase 'movmd'`
2			`# mach(): h8sx`
3			`# as(h8300): --defsym sim_cpu=0`
4			`# as(h8300h): --defsym sim_cpu=1`
5			`# as(h8300s): --defsym sim_cpu=2`
6			`# as(h8sx): --defsym sim_cpu=3`
7			`# ld(h8300h): -m h8300helf`
8			`# ld(h8300s): -m h8300self`
9			`# ld(h8sx): -m h8300sxelf`
10
11			`.include "testutils.inc"`
12
13			`.data`
14			`byte_src:`
15			`.byte 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16`
16			`byte_dst:`
17			`.byte 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0`
18
19			`.align 2`
20			`word_src:`
21			`.word 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16`
22			`word_dst:`
23			`.word 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0`
24
25			`.align 4`
26			`long_src:`
27			`.long 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16`
28			`long_dst:`
29			`.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0`
30
31			`start`
32			`.if (sim_cpu == h8sx)`
33			`movmd_b:#`
34			`# Byte block transfer`
35			`#`
36			`set_grs_a5a5`
37
38			`mov #byte_src, er5`
39			`mov #byte_dst, er6`
40			`mov #10, r4`
41			`set_ccr_zero`
42			`;; movmd.b`
43			`movmd.b`
44			`;;; .word 0x7b94`
45
46			`test_cc_clear`
47			`test_gr_a5a5 0`
48			`test_gr_a5a5 1`
49			`test_gr_a5a5 2`
50			`test_gr_a5a5 3`
51			`test_h_gr32 0xa5a50000 er4`
52			`test_h_gr32 byte_src+10 er5`
53			`test_h_gr32 byte_dst+10 er6`
54			`test_gr_a5a5 7`
55
56			`#`
57			`# Now make sure exactly 10 bytes were transferred.`
58			`memcmp byte_src byte_dst 10`
59			`cmp.b #0, @byte_dst+10`
60			`beq .L0`
61			`fail`
62			`.L0:`
63
64			`movmd_w:#`
65			`# Word block transfer`
66			`#`
67			`set_grs_a5a5`
68
69			`mov #word_src, er5`
70			`mov #word_dst, er6`
71			`mov #10, r4`
72			`set_ccr_zero`
73			`;; movmd.w`
74			`movmd.w`
75			`;;; .word 0x7ba4`
76
77			`test_cc_clear`
78			`test_gr_a5a5 0`
79			`test_gr_a5a5 1`
80			`test_gr_a5a5 2`
81			`test_gr_a5a5 3`
82			`test_h_gr32 0xa5a50000 er4`
83			`test_h_gr32 word_src+20 er5`
84			`test_h_gr32 word_dst+20 er6`
85			`test_gr_a5a5 7`
86
87			`#`
88			`# Now make sure exactly 20 bytes were transferred.`
89			`memcmp word_src word_dst 20`
90			`cmp.w #0, @word_dst+20`
91			`beq .L1`
92			`fail`
93			`.L1:`
94
95			`movmd_l:#`
96			`# Long block transfer`
97			`#`
98			`set_grs_a5a5`
99
100			`mov #long_src, er5`
101			`mov #long_dst, er6`
102			`mov #10, r4`
103			`set_ccr_zero`
104			`;; movmd.b`
105			`movmd.l`
106			`;;; .word 0x7bb4`
107
108			`test_cc_clear`
109			`test_gr_a5a5 0`
110			`test_gr_a5a5 1`
111			`test_gr_a5a5 2`
112			`test_gr_a5a5 3`
113			`test_h_gr32 0xa5a50000 er4`
114			`test_h_gr32 long_src+40 er5`
115			`test_h_gr32 long_dst+40 er6`
116			`test_gr_a5a5 7`
117
118			`#`
119			`# Now make sure exactly 40 bytes were transferred.`
120			`memcmp long_src long_dst 40`
121			`cmp.l #0, @long_dst+40`
122			`beq .L2`
123			`fail`
124			`.L2:`
125
126			`.endif`
127			`pass`
128
129			`exit 0`

Browse

Tools

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [movmd.s] - Blame information for rev 280