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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [orb.s] - Blame information for rev 225

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Line No. Rev Author Line
1 24 jeremybenn
# Hitachi H8 testcase 'or.b'
2
# mach(): all
3
# as(h8300):    --defsym sim_cpu=0
4
# as(h8300h):   --defsym sim_cpu=1
5
# as(h8300s):   --defsym sim_cpu=2
6
# as(h8sx):     --defsym sim_cpu=3
7
# ld(h8300h):   -m h8300helf
8
# ld(h8300s):   -m h8300self
9
# ld(h8sx):     -m h8300sxelf
10
 
11
        .include "testutils.inc"
12
 
13
        # Instructions tested:
14
        # or.b #xx:8, rd        ;                     c rd   xxxxxxxx
15
        # or.b #xx:8, @erd      ;         7 d rd ???? c ???? xxxxxxxx
16
        # or.b #xx:8, @erd+     ; 0 1 7 4 6 c rd 1??? c ???? xxxxxxxx
17
        # or.b #xx:8, @erd-     ; 0 1 7 6 6 c rd 1??? c ???? xxxxxxxx
18
        # or.b #xx:8, @+erd     ; 0 1 7 5 6 c rd 1??? c ???? xxxxxxxx
19
        # or.b #xx:8, @-erd     ; 0 1 7 7 6 c rd 1??? c ???? xxxxxxxx
20
        # or.b rs, rd           ;                     1 4 rs rd
21
        # or.b reg8, @erd       ;         7 d rd ???? 1 4 rs ????
22
        # or.b reg8, @erd+      ;         0 1 7     9 8 rd 4 rs
23
        # or.b reg8, @erd-      ;         0 1 7     9 a rd 4 rs
24
        # or.b reg8, @+erd      ;         0 1 7     9 9 rd 4 rs
25
        # or.b reg8, @-erd      ;         0 1 7     9 b rd 4 rs
26
        #
27
        # orc  #xx:8, ccr
28
        # orc  #xx:8, exr
29
 
30
 
31
        # Coming soon:
32
        # ...
33
 
34
.data
35
pre_byte:       .byte 0
36
byte_dest:      .byte 0xa5
37
post_byte:      .byte 0
38
 
39
        start
40
 
41
or_b_imm8_reg8:
42
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
43
        ;;  fixme set ccr
44
 
45
        ;;  or.b #xx:8,Rd
46
        or.b    #0xaa, r0l      ; Immediate 8-bit src, reg8 dest
47
 
48
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
49
        test_h_gr16 0xa5af r0   ; or result:    a5 | aa
50
.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
51
        test_h_gr32 0xa5a5a5af er0      ; or result:     a5 | aa
52
.endif
53
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
54
        test_gr_a5a5 2
55
        test_gr_a5a5 3
56
        test_gr_a5a5 4
57
        test_gr_a5a5 5
58
        test_gr_a5a5 6
59
        test_gr_a5a5 7
60
 
61
.if (sim_cpu == h8sx)
62
or_b_imm8_rdind:
63
        mov     #byte_dest, er0
64
        mov.b   #0xa5, r1l
65
        mov.b   r1l, @er0
66
 
67
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
68
        set_ccr_zero
69
 
70
        ;;  or.b #xx:8,@eRd
71
        mov     #byte_dest, er0
72
        or.b    #0xaa:8, @er0   ; Immediate 8-bit src, reg indirect dst
73
;;;     .word   0x7d00
74
;;;     .word   0xc0aa
75
 
76
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
77
        test_ovf_clear
78
        test_zero_clear
79
        test_neg_set
80
 
81
        test_h_gr32 byte_dest, er0      ; er0 still contains address
82
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
83
        test_gr_a5a5 2
84
        test_gr_a5a5 3
85
        test_gr_a5a5 4
86
        test_gr_a5a5 5
87
        test_gr_a5a5 6
88
        test_gr_a5a5 7
89
 
90
        ;; Now check the result of the or to memory.
91
        sub.b   r0l, r0l
92
        mov.b   @byte_dest, r0l
93
        cmp.b   #0xaf, r0l
94
        beq     .L1
95
        fail
96
.L1:
97
 
98
or_b_imm8_rdpostinc:
99
        mov     #byte_dest, er0
100
        mov.b   #0xa5, r1l
101
        mov.b   r1l, @er0
102
 
103
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
104
        set_ccr_zero
105
 
106
        ;;  or.b #xx:8,@eRd+
107
        mov     #byte_dest, er0
108
        or.b    #0x55:8, @er0+  ; Immediate 8-bit src, reg post-incr dest
109
;;;     .word   0x0174
110
;;;     .word   0x6c08
111
;;;     .word   0xc055
112
 
113
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
114
        test_ovf_clear
115
        test_zero_clear
116
        test_neg_set
117
 
118
        test_h_gr32 post_byte, er0      ; er0 contains address plus one
119
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
120
        test_gr_a5a5 2
121
        test_gr_a5a5 3
122
        test_gr_a5a5 4
123
        test_gr_a5a5 5
124
        test_gr_a5a5 6
125
        test_gr_a5a5 7
126
 
127
        ;; Now check the result of the or to memory.
128
        sub.b   r0l, r0l
129
        mov.b   @byte_dest, r0l
130
        cmp.b   #0xf5, r0l
131
        beq     .L2
132
        fail
133
.L2:
134
 
135
or_b_imm8_rdpostdec:
136
        mov     #byte_dest, er0
137
        mov.b   #0xa5, r1l
138
        mov.b   r1l, @er0
139
 
140
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
141
        set_ccr_zero
142
 
143
        ;;  or.b #xx:8,@eRd-
144
        mov     #byte_dest, er0
145
        or.b    #0xaa:8, @er0-  ; Immediate 8-bit src, reg post-decr dest
146
;;;     .word   0x0176
147
;;;     .word   0x6c08
148
;;;     .word   0xc0aa
149
 
150
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
151
        test_ovf_clear
152
        test_zero_clear
153
        test_neg_set
154
 
155
        test_h_gr32 pre_byte, er0       ; er0 contains address minus one
156
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
157
        test_gr_a5a5 2
158
        test_gr_a5a5 3
159
        test_gr_a5a5 4
160
        test_gr_a5a5 5
161
        test_gr_a5a5 6
162
        test_gr_a5a5 7
163
 
164
        ;; Now check the result of the or to memory.
165
        sub.b   r0l, r0l
166
        mov.b   @byte_dest, r0l
167
        cmp.b   #0xaf, r0l
168
        beq     .L3
169
        fail
170
.L3:
171
 
172
or_b_imm8_rdpreinc:
173
        mov     #byte_dest, er0
174
        mov.b   #0xa5, r1l
175
        mov.b   r1l, @er0
176
 
177
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
178
        set_ccr_zero
179
 
180
        ;;  or.b #xx:8,@+eRd
181
        mov     #pre_byte, er0
182
        or.b    #0x55:8, @+er0  ; Immediate 8-bit src, reg pre-incr dest
183
;;;     .word   0x0175
184
;;;     .word   0x6c08
185
;;;     .word   0xc055
186
 
187
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
188
        test_ovf_clear
189
        test_zero_clear
190
        test_neg_set
191
 
192
        test_h_gr32 byte_dest, er0      ; er0 contains destination address
193
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
194
        test_gr_a5a5 2
195
        test_gr_a5a5 3
196
        test_gr_a5a5 4
197
        test_gr_a5a5 5
198
        test_gr_a5a5 6
199
        test_gr_a5a5 7
200
 
201
        ;; Now check the result of the or to memory.
202
        sub.b   r0l, r0l
203
        mov.b   @byte_dest, r0l
204
        cmp.b   #0xf5, r0l
205
        beq     .L4
206
        fail
207
.L4:
208
 
209
or_b_imm8_rdpredec:
210
        mov     #byte_dest, er0
211
        mov.b   #0xa5, r1l
212
        mov.b   r1l, @er0
213
 
214
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
215
        set_ccr_zero
216
 
217
        ;;  or.b #xx:8,@-eRd
218
        mov     #post_byte, er0
219
        or.b    #0xaa:8, @-er0  ; Immediate 8-bit src, reg pre-decr dest
220
;;;     .word   0x0177
221
;;;     .word   0x6c08
222
;;;     .word   0xc0aa
223
 
224
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
225
        test_ovf_clear
226
        test_zero_clear
227
        test_neg_set
228
 
229
        test_h_gr32 byte_dest, er0      ; er0 contains destination address
230
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
231
        test_gr_a5a5 2
232
        test_gr_a5a5 3
233
        test_gr_a5a5 4
234
        test_gr_a5a5 5
235
        test_gr_a5a5 6
236
        test_gr_a5a5 7
237
 
238
        ;; Now check the result of the or to memory.
239
        sub.b   r0l, r0l
240
        mov.b   @byte_dest, r0l
241
        cmp.b   #0xaf, r0l
242
        beq     .L5
243
        fail
244
.L5:
245
 
246
 
247
.endif
248
 
249
or_b_reg8_reg8:
250
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
251
        ;;  fixme set ccr
252
 
253
        ;;  or.b Rs,Rd
254
        mov.b   #0xaa, r0h
255
        or.b    r0h, r0l        ; Reg8 src, reg8 dest
256
 
257
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
258
        test_h_gr16 0xaaaf r0   ; or result:    a5 | aa
259
.if (sim_cpu)                   ; non-zero means h8300h, s, or sx
260
        test_h_gr32 0xa5a5aaaf er0      ; or result:    a5 | aa
261
.endif
262
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
263
        test_gr_a5a5 2
264
        test_gr_a5a5 3
265
        test_gr_a5a5 4
266
        test_gr_a5a5 5
267
        test_gr_a5a5 6
268
        test_gr_a5a5 7
269
 
270
.if (sim_cpu == h8sx)
271
or_b_reg8_rdind:
272
        mov     #byte_dest, er0
273
        mov.b   #0xa5, r1l
274
        mov.b   r1l, @er0
275
 
276
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
277
        set_ccr_zero
278
 
279
        ;;  or.b rs8,@eRd       ; or reg8 to register indirect
280
        mov     #byte_dest, er0
281
        mov     #0xaa, r1l
282
        or.b    r1l, @er0       ; reg8 src, reg indirect dest
283
;;;     .word   0x7d00
284
;;;     .word   0x1490
285
 
286
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
287
        test_ovf_clear
288
        test_zero_clear
289
        test_neg_set
290
 
291
        test_h_gr32 byte_dest er0       ; er0 still contains address
292
        test_h_gr32 0xa5a5a5aa er1      ; er1 has the test load
293
 
294
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
295
        test_gr_a5a5 3
296
        test_gr_a5a5 4
297
        test_gr_a5a5 5
298
        test_gr_a5a5 6
299
        test_gr_a5a5 7
300
 
301
        ;; Now check the result of the or to memory.
302
        sub.b   r0l, r0l
303
        mov.b   @byte_dest, r0l
304
        cmp.b   #0xaf, r0l
305
        beq     .L6
306
        fail
307
.L6:
308
 
309
or_b_reg8_rdpostinc:
310
        mov     #byte_dest, er0
311
        mov.b   #0xa5, r1l
312
        mov.b   r1l, @er0
313
 
314
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
315
        set_ccr_zero
316
 
317
        ;;  or.b rs8,@eRd+      ; or reg8 to register indirect post-increment
318
        mov     #byte_dest, er0
319
        mov     #0x55, r1l
320
        or.b    r1l, @er0+      ; reg8 src, reg post-incr dest
321
;;;     .word   0x0179
322
;;;     .word   0x8049
323
 
324
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
325
        test_ovf_clear
326
        test_zero_clear
327
        test_neg_set
328
 
329
        test_h_gr32 post_byte er0       ; er0 contains address plus one
330
        test_h_gr32 0xa5a5a555 er1      ; er1 has the test load
331
 
332
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
333
        test_gr_a5a5 3
334
        test_gr_a5a5 4
335
        test_gr_a5a5 5
336
        test_gr_a5a5 6
337
        test_gr_a5a5 7
338
 
339
        ;; Now check the result of the or to memory.
340
        sub.b   r0l, r0l
341
        mov.b   @byte_dest, r0l
342
        cmp.b   #0xf5, r0l
343
        beq     .L7
344
        fail
345
.L7:
346
 
347
or_b_reg8_rdpostdec:
348
        mov     #byte_dest, er0
349
        mov.b   #0xa5, r1l
350
        mov.b   r1l, @er0
351
 
352
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
353
        set_ccr_zero
354
 
355
        ;;  or.b rs8,@eRd-      ; or reg8 to register indirect post-decrement
356
        mov     #byte_dest, er0
357
        mov     #0xaa, r1l
358
        or.b    r1l, @er0-      ; reg8 src, reg post-decr dest
359
;;;     .word   0x0179
360
;;;     .word   0xa049
361
 
362
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
363
        test_ovf_clear
364
        test_zero_clear
365
        test_neg_set
366
 
367
        test_h_gr32 pre_byte er0        ; er0 contains address minus one
368
        test_h_gr32 0xa5a5a5aa er1      ; er1 has the test load
369
 
370
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
371
        test_gr_a5a5 3
372
        test_gr_a5a5 4
373
        test_gr_a5a5 5
374
        test_gr_a5a5 6
375
        test_gr_a5a5 7
376
 
377
        ;; Now check the result of the or to memory.
378
        sub.b   r0l, r0l
379
        mov.b   @byte_dest, r0l
380
        cmp.b   #0xaf, r0l
381
        beq     .L8
382
        fail
383
.L8:
384
 
385
or_b_reg8_rdpreinc:
386
        mov     #byte_dest, er0
387
        mov.b   #0xa5, r1l
388
        mov.b   r1l, @er0
389
 
390
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
391
        set_ccr_zero
392
 
393
        ;;  or.b rs8,@+eRd      ; or reg8 to register indirect pre-increment
394
        mov     #pre_byte, er0
395
        mov     #0x55, r1l
396
        or.b    r1l, @+er0      ; reg8 src, reg pre-incr dest
397
;;;     .word   0x0179
398
;;;     .word   0x9049
399
 
400
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
401
        test_ovf_clear
402
        test_zero_clear
403
        test_neg_set
404
 
405
        test_h_gr32 byte_dest er0       ; er0 contains destination address
406
        test_h_gr32 0xa5a5a555 er1      ; er1 has the test load
407
 
408
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
409
        test_gr_a5a5 3
410
        test_gr_a5a5 4
411
        test_gr_a5a5 5
412
        test_gr_a5a5 6
413
        test_gr_a5a5 7
414
 
415
        ;; Now check the result of the or to memory.
416
        sub.b   r0l, r0l
417
        mov.b   @byte_dest, r0l
418
        cmp.b   #0xf5, r0l
419
        beq     .L9
420
        fail
421
.L9:
422
 
423
or_b_reg8_rdpredec:
424
        mov     #byte_dest, er0
425
        mov.b   #0xa5, r1l
426
        mov.b   r1l, @er0
427
 
428
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
429
        set_ccr_zero
430
 
431
        ;;  or.b rs8,@-eRd      ; or reg8 to register indirect pre-decrement
432
        mov     #post_byte, er0
433
        mov     #0xaa, r1l
434
        or.b    r1l, @-er0      ; reg8 src, reg pre-decr dest
435
;;;     .word   0x0179
436
;;;     .word   0xb049
437
 
438
        test_carry_clear        ; H=0 N=1 Z=0 V=0 C=0
439
        test_ovf_clear
440
        test_zero_clear
441
        test_neg_set
442
 
443
        test_h_gr32 byte_dest er0       ; er0 contains destination address
444
        test_h_gr32 0xa5a5a5aa er1      ; er1 has the test load
445
 
446
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
447
        test_gr_a5a5 3
448
        test_gr_a5a5 4
449
        test_gr_a5a5 5
450
        test_gr_a5a5 6
451
        test_gr_a5a5 7
452
 
453
        ;; Now check the result of the or to memory.
454
        sub.b   r0l, r0l
455
        mov.b   @byte_dest, r0l
456
        cmp.b   #0xaf, r0l
457
        beq     .L10
458
        fail
459
.L10:
460
 
461
.endif
462
 
463
orc_imm8_ccr:
464
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
465
        set_ccr_zero
466
 
467
        ;;  orc #xx:8,ccr
468
 
469
        test_neg_clear
470
        orc     #0x8, ccr       ; Immediate 8-bit operand (neg flag)
471
        test_neg_set
472
 
473
        test_zero_clear
474
        orc     #0x4, ccr       ; Immediate 8-bit operand (zero flag)
475
        test_zero_set
476
 
477
        test_ovf_clear
478
        orc     #0x2, ccr       ; Immediate 8-bit operand (overflow flag)
479
        test_ovf_set
480
 
481
        test_carry_clear
482
        orc     #0x1, ccr       ; Immediate 8-bit operand (carry flag)
483
        test_carry_set
484
 
485
        test_gr_a5a5 0           ; Make sure other general regs not disturbed
486
        test_gr_a5a5 1
487
        test_gr_a5a5 2
488
        test_gr_a5a5 3
489
        test_gr_a5a5 4
490
        test_gr_a5a5 5
491
        test_gr_a5a5 6
492
        test_gr_a5a5 7
493
 
494
.if (sim_cpu == h8300s || sim_cpu == h8sx)      ; Earlier versions, no exr
495
orc_imm8_exr:
496
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
497
 
498
        ldc     #0, exr
499
        stc     exr, r0l
500
        test_h_gr8 0, r0l
501
 
502
        ;;  orc #xx:8,exr
503
 
504
        orc     #0x1, exr
505
        stc     exr,r0l
506
        test_h_gr8 1, r0l
507
 
508
        orc     #0x2, exr
509
        stc     exr,r0l
510
        test_h_gr8 3, r0l
511
 
512
        orc     #0x4, exr
513
        stc     exr,r0l
514
        test_h_gr8 7, r0l
515
 
516
        orc     #0x80, exr
517
        stc     exr,r0l
518
        test_h_gr8 0x87, r0l
519
 
520
        test_h_gr32  0xa5a5a587 er0
521
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
522
        test_gr_a5a5 2
523
        test_gr_a5a5 3
524
        test_gr_a5a5 4
525
        test_gr_a5a5 5
526
        test_gr_a5a5 6
527
        test_gr_a5a5 7
528
.endif                          ; not h8300 or h8300h
529
 
530
        pass
531
 
532
        exit 0

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