OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [rotr.s] - Blame information for rev 24

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 24 jeremybenn 
# Hitachi H8 testcase 'rotr'
2 
# mach(): all
3 
# as(h8300):    --defsym sim_cpu=0
4 
# as(h8300h):   --defsym sim_cpu=1
5 
# as(h8300s):   --defsym sim_cpu=2
6 
# as(h8sx):     --defsym sim_cpu=3
7 
# ld(h8300h):   -m h8300helf
8 
# ld(h8300s):   -m h8300self
9 
# ld(h8sx):     -m h8300sxelf
10 
 
11 
        .include "testutils.inc"
12 
 
13 
        start
14 
 
15 
        .data
16 
byte_dest:      .byte   0xa5
17 
        .align 2
18 
word_dest:      .word   0xa5a5
19 
        .align 4
20 
long_dest:      .long   0xa5a5a5a5
21 
 
22 
        .text
23 
 
24 
rotr_b_reg8_1:
25 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
26 
        set_ccr_zero
27 
 
28 
        rotr.b  r0l             ; shift right arithmetic by one
29 
 
30 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
31 
        test_zero_clear
32 
        test_ovf_clear
33 
        test_neg_set
34 
 
35 
        test_h_gr16 0xa5d2 r0   ; 1010 0101 -> 1101 0010
36 
.if (sim_cpu)
37 
        test_h_gr32 0xa5a5a5d2 er0
38 
.endif
39 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
40 
        test_gr_a5a5 2
41 
        test_gr_a5a5 3
42 
        test_gr_a5a5 4
43 
        test_gr_a5a5 5
44 
        test_gr_a5a5 6
45 
        test_gr_a5a5 7
46 
 
47 
.if (sim_cpu == h8sx)
48 
rotr_b_ind_1:
49 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
50 
        set_ccr_zero
51 
 
52 
        mov     #byte_dest, er0
53 
        rotr.b  @er0    ; shift right arithmetic by one, indirect
54 
 
55 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
56 
        test_zero_clear
57 
        test_ovf_clear
58 
        test_neg_set
59 
 
60 
        test_h_gr32  byte_dest er0
61 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
62 
        test_gr_a5a5 2
63 
        test_gr_a5a5 3
64 
        test_gr_a5a5 4
65 
        test_gr_a5a5 5
66 
        test_gr_a5a5 6
67 
        test_gr_a5a5 7
68 
        ; 1010 0101 -> 1101 0010
69 
        cmp.b   #0xd2, @byte_dest
70 
        beq     .Lbind1
71 
        fail
72 
.Lbind1:
73 
        mov.b   #0xa5, @byte_dest
74 
 
75 
rotr_b_postinc_1:
76 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
77 
        set_ccr_zero
78 
 
79 
        mov     #byte_dest, er0
80 
        rotr.b  @er0+   ; shift right arithmetic by one, postinc
81 
 
82 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
83 
        test_zero_clear
84 
        test_ovf_clear
85 
        test_neg_set
86 
 
87 
        test_h_gr32  byte_dest+1 er0
88 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
89 
        test_gr_a5a5 2
90 
        test_gr_a5a5 3
91 
        test_gr_a5a5 4
92 
        test_gr_a5a5 5
93 
        test_gr_a5a5 6
94 
        test_gr_a5a5 7
95 
        ; 1010 0101 -> 1101 0010
96 
        cmp.b   #0xd2, @byte_dest
97 
        beq     .Lbpostinc1
98 
        fail
99 
.Lbpostinc1:
100 
        mov.b   #0xa5, @byte_dest
101 
 
102 
rotr_b_postdec_1:
103 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
104 
        set_ccr_zero
105 
 
106 
        mov     #byte_dest, er0
107 
        rotr.b  @er0-   ; shift right arithmetic by one, postdec
108 
 
109 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
110 
        test_zero_clear
111 
        test_ovf_clear
112 
        test_neg_set
113 
 
114 
        test_h_gr32  byte_dest-1 er0
115 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
116 
        test_gr_a5a5 2
117 
        test_gr_a5a5 3
118 
        test_gr_a5a5 4
119 
        test_gr_a5a5 5
120 
        test_gr_a5a5 6
121 
        test_gr_a5a5 7
122 
        ; 1010 0101 -> 1101 0010
123 
        cmp.b   #0xd2, @byte_dest
124 
        beq     .Lbpostdec1
125 
        fail
126 
.Lbpostdec1:
127 
        mov.b   #0xa5, @byte_dest
128 
 
129 
rotr_b_preinc_1:
130 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
131 
        set_ccr_zero
132 
 
133 
        mov     #byte_dest-1, er0
134 
        rotr.b  @+er0   ; shift right arithmetic by one, preinc
135 
 
136 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
137 
        test_zero_clear
138 
        test_ovf_clear
139 
        test_neg_set
140 
 
141 
        test_h_gr32  byte_dest er0
142 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
143 
        test_gr_a5a5 2
144 
        test_gr_a5a5 3
145 
        test_gr_a5a5 4
146 
        test_gr_a5a5 5
147 
        test_gr_a5a5 6
148 
        test_gr_a5a5 7
149 
        ; 1010 0101 -> 1101 0010
150 
        cmp.b   #0xd2, @byte_dest
151 
        beq     .Lbpreinc1
152 
        fail
153 
.Lbpreinc1:
154 
        mov.b   #0xa5, @byte_dest
155 
 
156 
rotr_b_predec_1:
157 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
158 
        set_ccr_zero
159 
 
160 
        mov     #byte_dest+1, er0
161 
        rotr.b  @-er0   ; shift right arithmetic by one, predec
162 
 
163 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
164 
        test_zero_clear
165 
        test_ovf_clear
166 
        test_neg_set
167 
 
168 
        test_h_gr32  byte_dest er0
169 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
170 
        test_gr_a5a5 2
171 
        test_gr_a5a5 3
172 
        test_gr_a5a5 4
173 
        test_gr_a5a5 5
174 
        test_gr_a5a5 6
175 
        test_gr_a5a5 7
176 
        ; 1010 0101 -> 1101 0010
177 
        cmp.b   #0xd2, @byte_dest
178 
        beq     .Lbpredec1
179 
        fail
180 
.Lbpredec1:
181 
        mov.b   #0xa5, @byte_dest
182 
 
183 
rotr_b_disp2_1:
184 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
185 
        set_ccr_zero
186 
 
187 
        mov     #byte_dest-2, er0
188 
        rotr.b  @(2:2, er0)     ; shift right arithmetic by one, disp2
189 
 
190 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
191 
        test_zero_clear
192 
        test_ovf_clear
193 
        test_neg_set
194 
 
195 
        test_h_gr32  byte_dest-2 er0
196 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
197 
        test_gr_a5a5 2
198 
        test_gr_a5a5 3
199 
        test_gr_a5a5 4
200 
        test_gr_a5a5 5
201 
        test_gr_a5a5 6
202 
        test_gr_a5a5 7
203 
        ; 1010 0101 -> 1101 0010
204 
        cmp.b   #0xd2, @byte_dest
205 
        beq     .Lbdisp21
206 
        fail
207 
.Lbdisp21:
208 
        mov.b   #0xa5, @byte_dest
209 
 
210 
rotr_b_disp16_1:
211 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
212 
        set_ccr_zero
213 
 
214 
        mov     #byte_dest-44, er0
215 
        rotr.b  @(44:16, er0)   ; shift right arithmetic by one, disp16
216 
 
217 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
218 
        test_zero_clear
219 
        test_ovf_clear
220 
        test_neg_set
221 
 
222 
        test_h_gr32  byte_dest-44 er0
223 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
224 
        test_gr_a5a5 2
225 
        test_gr_a5a5 3
226 
        test_gr_a5a5 4
227 
        test_gr_a5a5 5
228 
        test_gr_a5a5 6
229 
        test_gr_a5a5 7
230 
        ; 1010 0101 -> 1101 0010
231 
        cmp.b   #0xd2, @byte_dest
232 
        beq     .Lbdisp161
233 
        fail
234 
.Lbdisp161:
235 
        mov.b   #0xa5, @byte_dest
236 
 
237 
rotr_b_disp32_1:
238 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
239 
        set_ccr_zero
240 
 
241 
        mov     #byte_dest-666, er0
242 
        rotr.b  @(666:32, er0)  ; shift right arithmetic by one, disp32
243 
 
244 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
245 
        test_zero_clear
246 
        test_ovf_clear
247 
        test_neg_set
248 
 
249 
        test_h_gr32  byte_dest-666 er0
250 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
251 
        test_gr_a5a5 2
252 
        test_gr_a5a5 3
253 
        test_gr_a5a5 4
254 
        test_gr_a5a5 5
255 
        test_gr_a5a5 6
256 
        test_gr_a5a5 7
257 
        ; 1010 0101 -> 1101 0010
258 
        cmp.b   #0xd2, @byte_dest
259 
        beq     .Lbdisp321
260 
        fail
261 
.Lbdisp321:
262 
        mov.b   #0xa5, @byte_dest
263 
 
264 
rotr_b_abs16_1:
265 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
266 
        set_ccr_zero
267 
 
268 
        rotr.b  @byte_dest:16   ; shift right arithmetic by one, abs16
269 
 
270 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
271 
        test_zero_clear
272 
        test_ovf_clear
273 
        test_neg_set
274 
 
275 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
276 
        test_gr_a5a5 2
277 
        test_gr_a5a5 2
278 
        test_gr_a5a5 3
279 
        test_gr_a5a5 4
280 
        test_gr_a5a5 5
281 
        test_gr_a5a5 6
282 
        test_gr_a5a5 7
283 
        ; 1010 0101 -> 1101 0010
284 
        cmp.b   #0xd2, @byte_dest
285 
        beq     .Lbabs161
286 
        fail
287 
.Lbabs161:
288 
        mov.b   #0xa5, @byte_dest
289 
 
290 
rotr_b_abs32_1:
291 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
292 
        set_ccr_zero
293 
 
294 
        rotr.b  @byte_dest:32   ; shift right arithmetic by one, abs32
295 
 
296 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
297 
        test_zero_clear
298 
        test_ovf_clear
299 
        test_neg_set
300 
 
301 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
302 
        test_gr_a5a5 2
303 
        test_gr_a5a5 2
304 
        test_gr_a5a5 3
305 
        test_gr_a5a5 4
306 
        test_gr_a5a5 5
307 
        test_gr_a5a5 6
308 
        test_gr_a5a5 7
309 
        ; 1010 0101 -> 1101 0010
310 
        cmp.b   #0xd2, @byte_dest
311 
        beq     .Lbabs321
312 
        fail
313 
.Lbabs321:
314 
        mov.b   #0xa5, @byte_dest
315 
.endif
316 
 
317 
rotr_b_reg8_2:
318 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
319 
        set_ccr_zero
320 
 
321 
        rotr.b  #2, r0l         ; shift right arithmetic by two
322 
 
323 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
324 
        test_zero_clear
325 
        test_ovf_clear
326 
        test_neg_clear
327 
        test_h_gr16 0xa569 r0   ; 1010 0101 -> 0110 1001
328 
.if (sim_cpu)
329 
        test_h_gr32 0xa5a5a569 er0
330 
.endif
331 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
332 
        test_gr_a5a5 2
333 
        test_gr_a5a5 3
334 
        test_gr_a5a5 4
335 
        test_gr_a5a5 5
336 
        test_gr_a5a5 6
337 
        test_gr_a5a5 7
338 
 
339 
.if (sim_cpu == h8sx)
340 
rotr_b_ind_2:
341 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
342 
        set_ccr_zero
343 
 
344 
        mov     #byte_dest, er0
345 
        rotr.b  #2, @er0        ; shift right arithmetic by two, indirect
346 
 
347 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
348 
        test_zero_clear
349 
        test_ovf_clear
350 
        test_neg_clear
351 
 
352 
        test_h_gr32  byte_dest er0
353 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
354 
        test_gr_a5a5 2
355 
        test_gr_a5a5 3
356 
        test_gr_a5a5 4
357 
        test_gr_a5a5 5
358 
        test_gr_a5a5 6
359 
        test_gr_a5a5 7
360 
        ; 1010 0101 -> 0110 1001
361 
        cmp.b   #0x69, @byte_dest
362 
        beq     .Lbind2
363 
        fail
364 
.Lbind2:
365 
        mov.b   #0xa5, @byte_dest
366 
 
367 
rotr_b_postinc_2:
368 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
369 
        set_ccr_zero
370 
 
371 
        mov     #byte_dest, er0
372 
        rotr.b  #2, @er0+       ; shift right arithmetic by two, postinc
373 
 
374 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
375 
        test_zero_clear
376 
        test_ovf_clear
377 
        test_neg_clear
378 
 
379 
        test_h_gr32  byte_dest+1 er0
380 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
381 
        test_gr_a5a5 2
382 
        test_gr_a5a5 3
383 
        test_gr_a5a5 4
384 
        test_gr_a5a5 5
385 
        test_gr_a5a5 6
386 
        test_gr_a5a5 7
387 
        ; 1010 0101 -> 0110 1001
388 
        cmp.b   #0x69, @byte_dest
389 
        beq     .Lbpostinc2
390 
        fail
391 
.Lbpostinc2:
392 
        mov.b   #0xa5, @byte_dest
393 
 
394 
rotr_b_postdec_2:
395 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
396 
        set_ccr_zero
397 
 
398 
        mov     #byte_dest, er0
399 
        rotr.b  #2, @er0-       ; shift right arithmetic by two, postdec
400 
 
401 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
402 
        test_zero_clear
403 
        test_ovf_clear
404 
        test_neg_clear
405 
 
406 
        test_h_gr32  byte_dest-1 er0
407 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
408 
        test_gr_a5a5 2
409 
        test_gr_a5a5 3
410 
        test_gr_a5a5 4
411 
        test_gr_a5a5 5
412 
        test_gr_a5a5 6
413 
        test_gr_a5a5 7
414 
        ; 1010 0101 -> 0110 1001
415 
        cmp.b   #0x69, @byte_dest
416 
        beq     .Lbpostdec2
417 
        fail
418 
.Lbpostdec2:
419 
        mov.b   #0xa5, @byte_dest
420 
 
421 
rotr_b_preinc_2:
422 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
423 
        set_ccr_zero
424 
 
425 
        mov     #byte_dest-1, er0
426 
        rotr.b  #2, @+er0       ; shift right arithmetic by two, preinc
427 
 
428 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
429 
        test_zero_clear
430 
        test_ovf_clear
431 
        test_neg_clear
432 
 
433 
        test_h_gr32  byte_dest er0
434 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
435 
        test_gr_a5a5 2
436 
        test_gr_a5a5 3
437 
        test_gr_a5a5 4
438 
        test_gr_a5a5 5
439 
        test_gr_a5a5 6
440 
        test_gr_a5a5 7
441 
        ; 1010 0101 -> 0110 1001
442 
        cmp.b   #0x69, @byte_dest
443 
        beq     .Lbpreinc2
444 
        fail
445 
.Lbpreinc2:
446 
        mov.b   #0xa5, @byte_dest
447 
 
448 
rotr_b_predec_2:
449 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
450 
        set_ccr_zero
451 
 
452 
        mov     #byte_dest+1, er0
453 
        rotr.b  #2, @-er0       ; shift right arithmetic by two, predec
454 
 
455 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
456 
        test_zero_clear
457 
        test_ovf_clear
458 
        test_neg_clear
459 
 
460 
        test_h_gr32  byte_dest er0
461 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
462 
        test_gr_a5a5 2
463 
        test_gr_a5a5 3
464 
        test_gr_a5a5 4
465 
        test_gr_a5a5 5
466 
        test_gr_a5a5 6
467 
        test_gr_a5a5 7
468 
        ; 1010 0101 -> 0110 1001
469 
        cmp.b   #0x69, @byte_dest
470 
        beq     .Lbpredec2
471 
        fail
472 
.Lbpredec2:
473 
        mov.b   #0xa5, @byte_dest
474 
 
475 
rotr_b_disp2_2:
476 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
477 
        set_ccr_zero
478 
 
479 
        mov     #byte_dest-2, er0
480 
        rotr.b  #2, @(2:2, er0) ; shift right arithmetic by two, disp2
481 
 
482 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
483 
        test_zero_clear
484 
        test_ovf_clear
485 
        test_neg_clear
486 
 
487 
        test_h_gr32  byte_dest-2 er0
488 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
489 
        test_gr_a5a5 2
490 
        test_gr_a5a5 3
491 
        test_gr_a5a5 4
492 
        test_gr_a5a5 5
493 
        test_gr_a5a5 6
494 
        test_gr_a5a5 7
495 
        ; 1010 0101 -> 0110 1001
496 
        cmp.b   #0x69, @byte_dest
497 
        beq     .Lbdisp22
498 
        fail
499 
.Lbdisp22:
500 
        mov.b   #0xa5, @byte_dest
501 
 
502 
rotr_b_disp16_2:
503 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
504 
        set_ccr_zero
505 
 
506 
        mov     #byte_dest-44, er0
507 
        rotr.b  #2, @(44:16, er0)       ; shift right arithmetic by two, disp16
508 
 
509 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
510 
        test_zero_clear
511 
        test_ovf_clear
512 
        test_neg_clear
513 
 
514 
        test_h_gr32  byte_dest-44 er0
515 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
516 
        test_gr_a5a5 2
517 
        test_gr_a5a5 3
518 
        test_gr_a5a5 4
519 
        test_gr_a5a5 5
520 
        test_gr_a5a5 6
521 
        test_gr_a5a5 7
522 
        ; 1010 0101 -> 0110 1001
523 
        cmp.b   #0x69, @byte_dest
524 
        beq     .Lbdisp162
525 
        fail
526 
.Lbdisp162:
527 
        mov.b   #0xa5, @byte_dest
528 
 
529 
rotr_b_disp32_2:
530 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
531 
        set_ccr_zero
532 
 
533 
        mov     #byte_dest-666, er0
534 
        rotr.b  #2, @(666:32, er0)      ; shift right arithmetic by two, disp32
535 
 
536 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
537 
        test_zero_clear
538 
        test_ovf_clear
539 
        test_neg_clear
540 
 
541 
        test_h_gr32  byte_dest-666 er0
542 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
543 
        test_gr_a5a5 2
544 
        test_gr_a5a5 3
545 
        test_gr_a5a5 4
546 
        test_gr_a5a5 5
547 
        test_gr_a5a5 6
548 
        test_gr_a5a5 7
549 
        ; 1010 0101 -> 0110 1001
550 
        cmp.b   #0x69, @byte_dest
551 
        beq     .Lbdisp322
552 
        fail
553 
.Lbdisp322:
554 
        mov.b   #0xa5, @byte_dest
555 
 
556 
rotr_b_abs16_2:
557 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
558 
        set_ccr_zero
559 
 
560 
        rotr.b  #2, @byte_dest:16       ; shift right arithmetic by two, abs16
561 
 
562 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
563 
        test_zero_clear
564 
        test_ovf_clear
565 
        test_neg_clear
566 
 
567 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
568 
        test_gr_a5a5 2
569 
        test_gr_a5a5 2
570 
        test_gr_a5a5 3
571 
        test_gr_a5a5 4
572 
        test_gr_a5a5 5
573 
        test_gr_a5a5 6
574 
        test_gr_a5a5 7
575 
        ; 1010 0101 -> 0110 1001
576 
        cmp.b   #0x69, @byte_dest
577 
        beq     .Lbabs162
578 
        fail
579 
.Lbabs162:
580 
        mov.b   #0xa5, @byte_dest
581 
 
582 
rotr_b_abs32_2:
583 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
584 
        set_ccr_zero
585 
 
586 
        rotr.b  #2, @byte_dest:32       ; shift right arithmetic by two, abs32
587 
 
588 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
589 
        test_zero_clear
590 
        test_ovf_clear
591 
        test_neg_clear
592 
 
593 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
594 
        test_gr_a5a5 2
595 
        test_gr_a5a5 2
596 
        test_gr_a5a5 3
597 
        test_gr_a5a5 4
598 
        test_gr_a5a5 5
599 
        test_gr_a5a5 6
600 
        test_gr_a5a5 7
601 
        ; 1010 0101 -> 0110 1001
602 
        cmp.b   #0x69, @byte_dest
603 
        beq     .Lbabs322
604 
        fail
605 
.Lbabs322:
606 
        mov.b   #0xa5, @byte_dest
607 
.endif
608 
 
609 
.if (sim_cpu)                   ; Not available in h8300 mode
610 
rotr_w_reg16_1:
611 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
612 
        set_ccr_zero
613 
 
614 
        rotr.w  r0              ; shift right arithmetic by one
615 
 
616 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
617 
        test_zero_clear
618 
        test_ovf_clear
619 
        test_neg_set
620 
        test_h_gr16 0xd2d2 r0   ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
621 
        test_h_gr32 0xa5a5d2d2 er0
622 
 
623 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
624 
        test_gr_a5a5 2
625 
        test_gr_a5a5 3
626 
        test_gr_a5a5 4
627 
        test_gr_a5a5 5
628 
        test_gr_a5a5 6
629 
        test_gr_a5a5 7
630 
 
631 
.if (sim_cpu == h8sx)
632 
rotr_w_ind_1:
633 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
634 
        set_ccr_zero
635 
 
636 
        mov     #word_dest, er0
637 
        rotr.w  @er0    ; shift right arithmetic by one, indirect
638 
 
639 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
640 
        test_zero_clear
641 
        test_ovf_clear
642 
        test_neg_set
643 
 
644 
        test_h_gr32  word_dest er0
645 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
646 
        test_gr_a5a5 2
647 
        test_gr_a5a5 3
648 
        test_gr_a5a5 4
649 
        test_gr_a5a5 5
650 
        test_gr_a5a5 6
651 
        test_gr_a5a5 7
652 
        ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
653 
        cmp.w   #0xd2d2, @word_dest
654 
        beq     .Lwind1
655 
        fail
656 
.Lwind1:
657 
        mov.w   #0xa5a5, @word_dest
658 
 
659 
rotr_w_postinc_1:
660 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
661 
        set_ccr_zero
662 
 
663 
        mov     #word_dest, er0
664 
        rotr.w  @er0+   ; shift right arithmetic by one, postinc
665 
 
666 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
667 
        test_zero_clear
668 
        test_ovf_clear
669 
        test_neg_set
670 
 
671 
        test_h_gr32  word_dest+2 er0
672 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
673 
        test_gr_a5a5 2
674 
        test_gr_a5a5 3
675 
        test_gr_a5a5 4
676 
        test_gr_a5a5 5
677 
        test_gr_a5a5 6
678 
        test_gr_a5a5 7
679 
        ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
680 
        cmp.w   #0xd2d2, @word_dest
681 
        beq     .Lwpostinc1
682 
        fail
683 
.Lwpostinc1:
684 
        mov.w   #0xa5a5, @word_dest
685 
 
686 
rotr_w_postdec_1:
687 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
688 
        set_ccr_zero
689 
 
690 
        mov     #word_dest, er0
691 
        rotr.w  @er0-   ; shift right arithmetic by one, postdec
692 
 
693 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
694 
        test_zero_clear
695 
        test_ovf_clear
696 
        test_neg_set
697 
 
698 
        test_h_gr32  word_dest-2 er0
699 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
700 
        test_gr_a5a5 2
701 
        test_gr_a5a5 3
702 
        test_gr_a5a5 4
703 
        test_gr_a5a5 5
704 
        test_gr_a5a5 6
705 
        test_gr_a5a5 7
706 
        ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
707 
        cmp.w   #0xd2d2, @word_dest
708 
        beq     .Lwpostdec1
709 
        fail
710 
.Lwpostdec1:
711 
        mov.w   #0xa5a5, @word_dest
712 
 
713 
rotr_w_preinc_1:
714 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
715 
        set_ccr_zero
716 
 
717 
        mov     #word_dest-2, er0
718 
        rotr.w  @+er0   ; shift right arithmetic by one, preinc
719 
 
720 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
721 
        test_zero_clear
722 
        test_ovf_clear
723 
        test_neg_set
724 
 
725 
        test_h_gr32  word_dest er0
726 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
727 
        test_gr_a5a5 2
728 
        test_gr_a5a5 3
729 
        test_gr_a5a5 4
730 
        test_gr_a5a5 5
731 
        test_gr_a5a5 6
732 
        test_gr_a5a5 7
733 
        ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
734 
        cmp.w   #0xd2d2, @word_dest
735 
        beq     .Lwpreinc1
736 
        fail
737 
.Lwpreinc1:
738 
        mov.w   #0xa5a5, @word_dest
739 
 
740 
rotr_w_predec_1:
741 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
742 
        set_ccr_zero
743 
 
744 
        mov     #word_dest+2, er0
745 
        rotr.w  @-er0   ; shift right arithmetic by one, predec
746 
 
747 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
748 
        test_zero_clear
749 
        test_ovf_clear
750 
        test_neg_set
751 
 
752 
        test_h_gr32  word_dest er0
753 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
754 
        test_gr_a5a5 2
755 
        test_gr_a5a5 3
756 
        test_gr_a5a5 4
757 
        test_gr_a5a5 5
758 
        test_gr_a5a5 6
759 
        test_gr_a5a5 7
760 
        ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
761 
        cmp.w   #0xd2d2, @word_dest
762 
        beq     .Lwpredec1
763 
        fail
764 
.Lwpredec1:
765 
        mov.w   #0xa5a5, @word_dest
766 
 
767 
rotr_w_disp2_1:
768 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
769 
        set_ccr_zero
770 
 
771 
        mov     #word_dest-4, er0
772 
        rotr.w  @(4:2, er0)     ; shift right arithmetic by one, disp2
773 
 
774 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
775 
        test_zero_clear
776 
        test_ovf_clear
777 
        test_neg_set
778 
 
779 
        test_h_gr32  word_dest-4 er0
780 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
781 
        test_gr_a5a5 2
782 
        test_gr_a5a5 3
783 
        test_gr_a5a5 4
784 
        test_gr_a5a5 5
785 
        test_gr_a5a5 6
786 
        test_gr_a5a5 7
787 
        ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
788 
        cmp.w   #0xd2d2, @word_dest
789 
        beq     .Lwdisp21
790 
        fail
791 
.Lwdisp21:
792 
        mov.w   #0xa5a5, @word_dest
793 
 
794 
rotr_w_disp16_1:
795 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
796 
        set_ccr_zero
797 
 
798 
        mov     #word_dest-44, er0
799 
        rotr.w  @(44:16, er0)   ; shift right arithmetic by one, disp16
800 
 
801 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
802 
        test_zero_clear
803 
        test_ovf_clear
804 
        test_neg_set
805 
 
806 
        test_h_gr32  word_dest-44 er0
807 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
808 
        test_gr_a5a5 2
809 
        test_gr_a5a5 3
810 
        test_gr_a5a5 4
811 
        test_gr_a5a5 5
812 
        test_gr_a5a5 6
813 
        test_gr_a5a5 7
814 
        ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
815 
        cmp.w   #0xd2d2, @word_dest
816 
        beq     .Lwdisp161
817 
        fail
818 
.Lwdisp161:
819 
        mov.w   #0xa5a5, @word_dest
820 
 
821 
rotr_w_disp32_1:
822 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
823 
        set_ccr_zero
824 
 
825 
        mov     #word_dest-666, er0
826 
        rotr.w  @(666:32, er0)  ; shift right arithmetic by one, disp32
827 
 
828 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
829 
        test_zero_clear
830 
        test_ovf_clear
831 
        test_neg_set
832 
 
833 
        test_h_gr32  word_dest-666 er0
834 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
835 
        test_gr_a5a5 2
836 
        test_gr_a5a5 3
837 
        test_gr_a5a5 4
838 
        test_gr_a5a5 5
839 
        test_gr_a5a5 6
840 
        test_gr_a5a5 7
841 
        ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
842 
        cmp.w   #0xd2d2, @word_dest
843 
        beq     .Lwdisp321
844 
        fail
845 
.Lwdisp321:
846 
        mov.w   #0xa5a5, @word_dest
847 
 
848 
rotr_w_abs16_1:
849 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
850 
        set_ccr_zero
851 
 
852 
        rotr.w  @word_dest:16   ; shift right arithmetic by one, abs16
853 
 
854 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
855 
        test_zero_clear
856 
        test_ovf_clear
857 
        test_neg_set
858 
 
859 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
860 
        test_gr_a5a5 1
861 
        test_gr_a5a5 2
862 
        test_gr_a5a5 3
863 
        test_gr_a5a5 4
864 
        test_gr_a5a5 5
865 
        test_gr_a5a5 6
866 
        test_gr_a5a5 7
867 
        ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
868 
        cmp.w   #0xd2d2, @word_dest
869 
        beq     .Lwabs161
870 
        fail
871 
.Lwabs161:
872 
        mov.w   #0xa5a5, @word_dest
873 
 
874 
rotr_w_abs32_1:
875 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
876 
        set_ccr_zero
877 
 
878 
        rotr.w  @word_dest:32   ; shift right arithmetic by one, abs32
879 
 
880 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
881 
        test_zero_clear
882 
        test_ovf_clear
883 
        test_neg_set
884 
 
885 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
886 
        test_gr_a5a5 1
887 
        test_gr_a5a5 2
888 
        test_gr_a5a5 3
889 
        test_gr_a5a5 4
890 
        test_gr_a5a5 5
891 
        test_gr_a5a5 6
892 
        test_gr_a5a5 7
893 
        ; 1010 0101 1010 0101 -> 1101 0010 1101 0010
894 
        cmp.w   #0xd2d2, @word_dest
895 
        beq     .Lwabs321
896 
        fail
897 
.Lwabs321:
898 
        mov.w   #0xa5a5, @word_dest
899 
.endif
900 
 
901 
rotr_w_reg16_2:
902 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
903 
        set_ccr_zero
904 
 
905 
        rotr.w  #2, r0          ; shift right arithmetic by two
906 
 
907 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
908 
        test_zero_clear
909 
        test_ovf_clear
910 
        test_neg_clear
911 
 
912 
        test_h_gr16 0x6969 r0   ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
913 
        test_h_gr32 0xa5a56969 er0
914 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
915 
        test_gr_a5a5 2
916 
        test_gr_a5a5 3
917 
        test_gr_a5a5 4
918 
        test_gr_a5a5 5
919 
        test_gr_a5a5 6
920 
        test_gr_a5a5 7
921 
 
922 
.if (sim_cpu == h8sx)
923 
rotr_w_ind_2:
924 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
925 
        set_ccr_zero
926 
 
927 
        mov     #word_dest, er0
928 
        rotr.w  #2, @er0        ; shift right arithmetic by two, indirect
929 
 
930 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
931 
        test_zero_clear
932 
        test_ovf_clear
933 
        test_neg_clear
934 
 
935 
        test_h_gr32  word_dest er0
936 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
937 
        test_gr_a5a5 2
938 
        test_gr_a5a5 3
939 
        test_gr_a5a5 4
940 
        test_gr_a5a5 5
941 
        test_gr_a5a5 6
942 
        test_gr_a5a5 7
943 
        ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
944 
        cmp.w   #0x6969, @word_dest
945 
        beq     .Lwind2
946 
        fail
947 
.Lwind2:
948 
        mov.w   #0xa5a5, @word_dest
949 
 
950 
rotr_w_postinc_2:
951 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
952 
        set_ccr_zero
953 
 
954 
        mov     #word_dest, er0
955 
        rotr.w  #2, @er0+       ; shift right arithmetic by two, postinc
956 
 
957 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
958 
        test_zero_clear
959 
        test_ovf_clear
960 
        test_neg_clear
961 
 
962 
        test_h_gr32  word_dest+2 er0
963 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
964 
        test_gr_a5a5 2
965 
        test_gr_a5a5 3
966 
        test_gr_a5a5 4
967 
        test_gr_a5a5 5
968 
        test_gr_a5a5 6
969 
        test_gr_a5a5 7
970 
        ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
971 
        cmp.w   #0x6969, @word_dest
972 
        beq     .Lwpostinc2
973 
        fail
974 
.Lwpostinc2:
975 
        mov.w   #0xa5a5, @word_dest
976 
 
977 
rotr_w_postdec_2:
978 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
979 
        set_ccr_zero
980 
 
981 
        mov     #word_dest, er0
982 
        rotr.w  #2, @er0-       ; shift right arithmetic by two, postdec
983 
 
984 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
985 
        test_zero_clear
986 
        test_ovf_clear
987 
        test_neg_clear
988 
 
989 
        test_h_gr32  word_dest-2 er0
990 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
991 
        test_gr_a5a5 2
992 
        test_gr_a5a5 3
993 
        test_gr_a5a5 4
994 
        test_gr_a5a5 5
995 
        test_gr_a5a5 6
996 
        test_gr_a5a5 7
997 
        ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
998 
        cmp.w   #0x6969, @word_dest
999 
        beq     .Lwpostdec2
1000 
        fail
1001 
.Lwpostdec2:
1002 
        mov.w   #0xa5a5, @word_dest
1003 
 
1004 
rotr_w_preinc_2:
1005 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1006 
        set_ccr_zero
1007 
 
1008 
        mov     #word_dest-2, er0
1009 
        rotr.w  #2, @+er0       ; shift right arithmetic by two, preinc
1010 
 
1011 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1012 
        test_zero_clear
1013 
        test_ovf_clear
1014 
        test_neg_clear
1015 
 
1016 
        test_h_gr32  word_dest er0
1017 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1018 
        test_gr_a5a5 2
1019 
        test_gr_a5a5 3
1020 
        test_gr_a5a5 4
1021 
        test_gr_a5a5 5
1022 
        test_gr_a5a5 6
1023 
        test_gr_a5a5 7
1024 
        ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1025 
        cmp.w   #0x6969, @word_dest
1026 
        beq     .Lwpreinc2
1027 
        fail
1028 
.Lwpreinc2:
1029 
        mov.w   #0xa5a5, @word_dest
1030 
 
1031 
rotr_w_predec_2:
1032 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1033 
        set_ccr_zero
1034 
 
1035 
        mov     #word_dest+2, er0
1036 
        rotr.w  #2, @-er0       ; shift right arithmetic by two, predec
1037 
 
1038 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1039 
        test_zero_clear
1040 
        test_ovf_clear
1041 
        test_neg_clear
1042 
 
1043 
        test_h_gr32  word_dest er0
1044 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1045 
        test_gr_a5a5 2
1046 
        test_gr_a5a5 3
1047 
        test_gr_a5a5 4
1048 
        test_gr_a5a5 5
1049 
        test_gr_a5a5 6
1050 
        test_gr_a5a5 7
1051 
        ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1052 
        cmp.w   #0x6969, @word_dest
1053 
        beq     .Lwpredec2
1054 
        fail
1055 
.Lwpredec2:
1056 
        mov.w   #0xa5a5, @word_dest
1057 
 
1058 
rotr_w_disp2_2:
1059 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1060 
        set_ccr_zero
1061 
 
1062 
        mov     #word_dest-4, er0
1063 
        rotr.w  #2, @(4:2, er0) ; shift right arithmetic by two, disp2
1064 
 
1065 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1066 
        test_zero_clear
1067 
        test_ovf_clear
1068 
        test_neg_clear
1069 
 
1070 
        test_h_gr32  word_dest-4 er0
1071 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1072 
        test_gr_a5a5 2
1073 
        test_gr_a5a5 3
1074 
        test_gr_a5a5 4
1075 
        test_gr_a5a5 5
1076 
        test_gr_a5a5 6
1077 
        test_gr_a5a5 7
1078 
        ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1079 
        cmp.w   #0x6969, @word_dest
1080 
        beq     .Lwdisp22
1081 
        fail
1082 
.Lwdisp22:
1083 
        mov.w   #0xa5a5, @word_dest
1084 
 
1085 
rotr_w_disp16_2:
1086 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1087 
        set_ccr_zero
1088 
 
1089 
        mov     #word_dest-44, er0
1090 
        rotr.w  #2, @(44:16, er0)       ; shift right arithmetic by two, disp16
1091 
 
1092 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1093 
        test_zero_clear
1094 
        test_ovf_clear
1095 
        test_neg_clear
1096 
 
1097 
        test_h_gr32  word_dest-44 er0
1098 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1099 
        test_gr_a5a5 2
1100 
        test_gr_a5a5 3
1101 
        test_gr_a5a5 4
1102 
        test_gr_a5a5 5
1103 
        test_gr_a5a5 6
1104 
        test_gr_a5a5 7
1105 
        ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1106 
        cmp.w   #0x6969, @word_dest
1107 
        beq     .Lwdisp162
1108 
        fail
1109 
.Lwdisp162:
1110 
        mov.w   #0xa5a5, @word_dest
1111 
 
1112 
rotr_w_disp32_2:
1113 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1114 
        set_ccr_zero
1115 
 
1116 
        mov     #word_dest-666, er0
1117 
        rotr.w  #2, @(666:32, er0)      ; shift right arithmetic by two, disp32
1118 
 
1119 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1120 
        test_zero_clear
1121 
        test_ovf_clear
1122 
        test_neg_clear
1123 
 
1124 
        test_h_gr32  word_dest-666 er0
1125 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1126 
        test_gr_a5a5 2
1127 
        test_gr_a5a5 3
1128 
        test_gr_a5a5 4
1129 
        test_gr_a5a5 5
1130 
        test_gr_a5a5 6
1131 
        test_gr_a5a5 7
1132 
        ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1133 
        cmp.w   #0x6969, @word_dest
1134 
        beq     .Lwdisp322
1135 
        fail
1136 
.Lwdisp322:
1137 
        mov.w   #0xa5a5, @word_dest
1138 
 
1139 
rotr_w_abs16_2:
1140 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1141 
        set_ccr_zero
1142 
 
1143 
        rotr.w  #2, @word_dest:16       ; shift right arithmetic by two, abs16
1144 
 
1145 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1146 
        test_zero_clear
1147 
        test_ovf_clear
1148 
        test_neg_clear
1149 
 
1150 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
1151 
        test_gr_a5a5 2
1152 
        test_gr_a5a5 2
1153 
        test_gr_a5a5 3
1154 
        test_gr_a5a5 4
1155 
        test_gr_a5a5 5
1156 
        test_gr_a5a5 6
1157 
        test_gr_a5a5 7
1158 
        ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1159 
        cmp.w   #0x6969, @word_dest
1160 
        beq     .Lwabs162
1161 
        fail
1162 
.Lwabs162:
1163 
        mov.w   #0xa5a5, @word_dest
1164 
 
1165 
rotr_w_abs32_2:
1166 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1167 
        set_ccr_zero
1168 
 
1169 
        rotr.w  #2, @word_dest:32       ; shift right arithmetic by two, abs32
1170 
 
1171 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1172 
        test_zero_clear
1173 
        test_ovf_clear
1174 
        test_neg_clear
1175 
 
1176 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
1177 
        test_gr_a5a5 2
1178 
        test_gr_a5a5 2
1179 
        test_gr_a5a5 3
1180 
        test_gr_a5a5 4
1181 
        test_gr_a5a5 5
1182 
        test_gr_a5a5 6
1183 
        test_gr_a5a5 7
1184 
        ; 1010 0101 1010 0101 -> 0110 1001 0110 1001
1185 
        cmp.w   #0x6969, @word_dest
1186 
        beq     .Lwabs322
1187 
        fail
1188 
.Lwabs322:
1189 
        mov.w   #0xa5a5, @word_dest
1190 
.endif
1191 
 
1192 
rotr_l_reg32_1:
1193 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1194 
        set_ccr_zero
1195 
 
1196 
        rotr.l  er0             ; shift right arithmetic by one, register
1197 
 
1198 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1199 
        test_zero_clear
1200 
        test_ovf_clear
1201 
        test_neg_set
1202 
 
1203 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1204 
        ; -> 1101 0010 1101 0010 1101 0010 1101 0010
1205 
        test_h_gr32  0xd2d2d2d2 er0
1206 
 
1207 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1208 
        test_gr_a5a5 2
1209 
        test_gr_a5a5 3
1210 
        test_gr_a5a5 4
1211 
        test_gr_a5a5 5
1212 
        test_gr_a5a5 6
1213 
        test_gr_a5a5 7
1214 
 
1215 
.if (sim_cpu == h8sx)
1216 
rotr_l_ind_1:
1217 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1218 
        set_ccr_zero
1219 
 
1220 
        mov     #long_dest, er0
1221 
        rotr.l  @er0    ; shift right arithmetic by one, indirect
1222 
 
1223 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1224 
        test_zero_clear
1225 
        test_ovf_clear
1226 
        test_neg_set
1227 
 
1228 
        test_h_gr32  long_dest er0
1229 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1230 
        test_gr_a5a5 2
1231 
        test_gr_a5a5 3
1232 
        test_gr_a5a5 4
1233 
        test_gr_a5a5 5
1234 
        test_gr_a5a5 6
1235 
        test_gr_a5a5 7
1236 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1237 
        ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1238 
        cmp.l   #0xd2d2d2d2, @long_dest
1239 
        beq     .Llind1
1240 
        fail
1241 
.Llind1:
1242 
        mov     #0xa5a5a5a5, @long_dest
1243 
 
1244 
rotr_l_postinc_1:
1245 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1246 
        set_ccr_zero
1247 
 
1248 
        mov     #long_dest, er0
1249 
        rotr.l  @er0+   ; shift right arithmetic by one, postinc
1250 
 
1251 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1252 
        test_zero_clear
1253 
        test_ovf_clear
1254 
        test_neg_set
1255 
 
1256 
        test_h_gr32  long_dest+4 er0
1257 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1258 
        test_gr_a5a5 2
1259 
        test_gr_a5a5 3
1260 
        test_gr_a5a5 4
1261 
        test_gr_a5a5 5
1262 
        test_gr_a5a5 6
1263 
        test_gr_a5a5 7
1264 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1265 
        ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1266 
        cmp.l   #0xd2d2d2d2, @long_dest
1267 
        beq     .Llpostinc1
1268 
        fail
1269 
.Llpostinc1:
1270 
        mov     #0xa5a5a5a5, @long_dest
1271 
 
1272 
rotr_l_postdec_1:
1273 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1274 
        set_ccr_zero
1275 
 
1276 
        mov     #long_dest, er0
1277 
        rotr.l  @er0-   ; shift right arithmetic by one, postdec
1278 
 
1279 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1280 
        test_zero_clear
1281 
        test_ovf_clear
1282 
        test_neg_set
1283 
 
1284 
        test_h_gr32  long_dest-4 er0
1285 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1286 
        test_gr_a5a5 2
1287 
        test_gr_a5a5 3
1288 
        test_gr_a5a5 4
1289 
        test_gr_a5a5 5
1290 
        test_gr_a5a5 6
1291 
        test_gr_a5a5 7
1292 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1293 
        ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1294 
        cmp.l   #0xd2d2d2d2, @long_dest
1295 
        beq     .Llpostdec1
1296 
        fail
1297 
.Llpostdec1:
1298 
        mov     #0xa5a5a5a5, @long_dest
1299 
 
1300 
rotr_l_preinc_1:
1301 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1302 
        set_ccr_zero
1303 
 
1304 
        mov     #long_dest-4, er0
1305 
        rotr.l  @+er0   ; shift right arithmetic by one, preinc
1306 
 
1307 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1308 
        test_zero_clear
1309 
        test_ovf_clear
1310 
        test_neg_set
1311 
 
1312 
        test_h_gr32  long_dest er0
1313 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1314 
        test_gr_a5a5 2
1315 
        test_gr_a5a5 3
1316 
        test_gr_a5a5 4
1317 
        test_gr_a5a5 5
1318 
        test_gr_a5a5 6
1319 
        test_gr_a5a5 7
1320 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1321 
        ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1322 
        cmp.l   #0xd2d2d2d2, @long_dest
1323 
        beq     .Llpreinc1
1324 
        fail
1325 
.Llpreinc1:
1326 
        mov     #0xa5a5a5a5, @long_dest
1327 
 
1328 
rotr_l_predec_1:
1329 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1330 
        set_ccr_zero
1331 
 
1332 
        mov     #long_dest+4, er0
1333 
        rotr.l  @-er0   ; shift right arithmetic by one, predec
1334 
 
1335 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1336 
        test_zero_clear
1337 
        test_ovf_clear
1338 
        test_neg_set
1339 
 
1340 
        test_h_gr32  long_dest er0
1341 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1342 
        test_gr_a5a5 2
1343 
        test_gr_a5a5 3
1344 
        test_gr_a5a5 4
1345 
        test_gr_a5a5 5
1346 
        test_gr_a5a5 6
1347 
        test_gr_a5a5 7
1348 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1349 
        ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1350 
        cmp.l   #0xd2d2d2d2, @long_dest
1351 
        beq     .Llpredec1
1352 
        fail
1353 
.Llpredec1:
1354 
        mov     #0xa5a5a5a5, @long_dest
1355 
 
1356 
rotr_l_disp2_1:
1357 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1358 
        set_ccr_zero
1359 
 
1360 
        mov     #long_dest-8, er0
1361 
        rotr.l  @(8:2, er0)     ; shift right arithmetic by one, disp2
1362 
 
1363 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1364 
        test_zero_clear
1365 
        test_ovf_clear
1366 
        test_neg_set
1367 
 
1368 
        test_h_gr32  long_dest-8 er0
1369 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1370 
        test_gr_a5a5 2
1371 
        test_gr_a5a5 3
1372 
        test_gr_a5a5 4
1373 
        test_gr_a5a5 5
1374 
        test_gr_a5a5 6
1375 
        test_gr_a5a5 7
1376 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1377 
        ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1378 
        cmp.l   #0xd2d2d2d2, @long_dest
1379 
        beq     .Lldisp21
1380 
        fail
1381 
.Lldisp21:
1382 
        mov     #0xa5a5a5a5, @long_dest
1383 
 
1384 
rotr_l_disp16_1:
1385 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1386 
        set_ccr_zero
1387 
 
1388 
        mov     #long_dest-44, er0
1389 
        rotr.l  @(44:16, er0)   ; shift right arithmetic by one, disp16
1390 
 
1391 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1392 
        test_zero_clear
1393 
        test_ovf_clear
1394 
        test_neg_set
1395 
 
1396 
        test_h_gr32  long_dest-44 er0
1397 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1398 
        test_gr_a5a5 2
1399 
        test_gr_a5a5 3
1400 
        test_gr_a5a5 4
1401 
        test_gr_a5a5 5
1402 
        test_gr_a5a5 6
1403 
        test_gr_a5a5 7
1404 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1405 
        ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1406 
        cmp.l   #0xd2d2d2d2, @long_dest
1407 
        beq     .Lldisp161
1408 
        fail
1409 
.Lldisp161:
1410 
        mov     #0xa5a5a5a5, @long_dest
1411 
 
1412 
rotr_l_disp32_1:
1413 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1414 
        set_ccr_zero
1415 
 
1416 
        mov     #long_dest-666, er0
1417 
        rotr.l  @(666:32, er0)  ; shift right arithmetic by one, disp32
1418 
 
1419 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1420 
        test_zero_clear
1421 
        test_ovf_clear
1422 
        test_neg_set
1423 
 
1424 
        test_h_gr32  long_dest-666 er0
1425 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1426 
        test_gr_a5a5 2
1427 
        test_gr_a5a5 3
1428 
        test_gr_a5a5 4
1429 
        test_gr_a5a5 5
1430 
        test_gr_a5a5 6
1431 
        test_gr_a5a5 7
1432 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1433 
        ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1434 
        cmp.l   #0xd2d2d2d2, @long_dest
1435 
        beq     .Lldisp321
1436 
        fail
1437 
.Lldisp321:
1438 
        mov     #0xa5a5a5a5, @long_dest
1439 
 
1440 
rotr_l_abs16_1:
1441 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1442 
        set_ccr_zero
1443 
 
1444 
        rotr.l  @long_dest:16   ; shift right arithmetic by one, abs16
1445 
 
1446 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1447 
        test_zero_clear
1448 
        test_ovf_clear
1449 
        test_neg_set
1450 
 
1451 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
1452 
        test_gr_a5a5 1
1453 
        test_gr_a5a5 2
1454 
        test_gr_a5a5 3
1455 
        test_gr_a5a5 4
1456 
        test_gr_a5a5 5
1457 
        test_gr_a5a5 6
1458 
        test_gr_a5a5 7
1459 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1460 
        ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1461 
        cmp.l   #0xd2d2d2d2, @long_dest
1462 
        beq     .Llabs161
1463 
        fail
1464 
.Llabs161:
1465 
        mov     #0xa5a5a5a5, @long_dest
1466 
 
1467 
rotr_l_abs32_1:
1468 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1469 
        set_ccr_zero
1470 
 
1471 
        rotr.l  @long_dest:32   ; shift right arithmetic by one, abs32
1472 
 
1473 
        test_carry_set          ; H=0 N=1 Z=0 V=0 C=1
1474 
        test_zero_clear
1475 
        test_ovf_clear
1476 
        test_neg_set
1477 
 
1478 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
1479 
        test_gr_a5a5 1
1480 
        test_gr_a5a5 2
1481 
        test_gr_a5a5 3
1482 
        test_gr_a5a5 4
1483 
        test_gr_a5a5 5
1484 
        test_gr_a5a5 6
1485 
        test_gr_a5a5 7
1486 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1487 
        ;; -> 1101 0010 1101 0010 1101 0010 1101 0010
1488 
        cmp.l   #0xd2d2d2d2, @long_dest
1489 
        beq     .Llabs321
1490 
        fail
1491 
.Llabs321:
1492 
        mov     #0xa5a5a5a5, @long_dest
1493 
.endif
1494 
 
1495 
rotr_l_reg32_2:
1496 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1497 
        set_ccr_zero
1498 
 
1499 
        rotr.l  #2, er0         ; shift right arithmetic by two, register
1500 
 
1501 
        test_carry_clear        ; H=0 N=0 Z=0 V=0 C=0
1502 
        test_zero_clear
1503 
        test_ovf_clear
1504 
        test_neg_clear
1505 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1506 
        ; -> 0110 1001 0110 1001 0110 1001 0110 1001
1507 
        test_h_gr32  0x69696969 er0
1508 
 
1509 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1510 
        test_gr_a5a5 2
1511 
        test_gr_a5a5 3
1512 
        test_gr_a5a5 4
1513 
        test_gr_a5a5 5
1514 
        test_gr_a5a5 6
1515 
        test_gr_a5a5 7
1516 
 
1517 
.if (sim_cpu == h8sx)
1518 
 
1519 
rotr_l_ind_2:
1520 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1521 
        set_ccr_zero
1522 
 
1523 
        mov     #long_dest, er0
1524 
        rotr.l  #2, @er0        ; shift right arithmetic by two, indirect
1525 
 
1526 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1527 
        test_zero_clear
1528 
        test_ovf_clear
1529 
        test_neg_clear
1530 
 
1531 
        test_h_gr32  long_dest er0
1532 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1533 
        test_gr_a5a5 2
1534 
        test_gr_a5a5 3
1535 
        test_gr_a5a5 4
1536 
        test_gr_a5a5 5
1537 
        test_gr_a5a5 6
1538 
        test_gr_a5a5 7
1539 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1540 
        ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1541 
        cmp.l   #0x69696969, @long_dest
1542 
        beq     .Llind2
1543 
        fail
1544 
.Llind2:
1545 
        mov     #0xa5a5a5a5, @long_dest
1546 
 
1547 
rotr_l_postinc_2:
1548 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1549 
        set_ccr_zero
1550 
 
1551 
        mov     #long_dest, er0
1552 
        rotr.l  #2, @er0+       ; shift right arithmetic by two, postinc
1553 
 
1554 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1555 
        test_zero_clear
1556 
        test_ovf_clear
1557 
        test_neg_clear
1558 
 
1559 
        test_h_gr32  long_dest+4 er0
1560 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1561 
        test_gr_a5a5 2
1562 
        test_gr_a5a5 3
1563 
        test_gr_a5a5 4
1564 
        test_gr_a5a5 5
1565 
        test_gr_a5a5 6
1566 
        test_gr_a5a5 7
1567 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1568 
        ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1569 
        cmp.l   #0x69696969, @long_dest
1570 
        beq     .Llpostinc2
1571 
        fail
1572 
.Llpostinc2:
1573 
        mov     #0xa5a5a5a5, @long_dest
1574 
 
1575 
rotr_l_postdec_2:
1576 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1577 
        set_ccr_zero
1578 
 
1579 
        mov     #long_dest, er0
1580 
        rotr.l  #2, @er0-       ; shift right arithmetic by two, postdec
1581 
 
1582 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1583 
        test_zero_clear
1584 
        test_ovf_clear
1585 
        test_neg_clear
1586 
 
1587 
        test_h_gr32  long_dest-4 er0
1588 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1589 
        test_gr_a5a5 2
1590 
        test_gr_a5a5 3
1591 
        test_gr_a5a5 4
1592 
        test_gr_a5a5 5
1593 
        test_gr_a5a5 6
1594 
        test_gr_a5a5 7
1595 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1596 
        ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1597 
        cmp.l   #0x69696969, @long_dest
1598 
        beq     .Llpostdec2
1599 
        fail
1600 
.Llpostdec2:
1601 
        mov     #0xa5a5a5a5, @long_dest
1602 
 
1603 
rotr_l_preinc_2:
1604 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1605 
        set_ccr_zero
1606 
 
1607 
        mov     #long_dest-4, er0
1608 
        rotr.l  #2, @+er0       ; shift right arithmetic by two, preinc
1609 
 
1610 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1611 
        test_zero_clear
1612 
        test_ovf_clear
1613 
        test_neg_clear
1614 
 
1615 
        test_h_gr32  long_dest er0
1616 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1617 
        test_gr_a5a5 2
1618 
        test_gr_a5a5 3
1619 
        test_gr_a5a5 4
1620 
        test_gr_a5a5 5
1621 
        test_gr_a5a5 6
1622 
        test_gr_a5a5 7
1623 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1624 
        ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1625 
        cmp.l   #0x69696969, @long_dest
1626 
        beq     .Llpreinc2
1627 
        fail
1628 
.Llpreinc2:
1629 
        mov     #0xa5a5a5a5, @long_dest
1630 
 
1631 
rotr_l_predec_2:
1632 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1633 
        set_ccr_zero
1634 
 
1635 
        mov     #long_dest+4, er0
1636 
        rotr.l  #2, @-er0       ; shift right arithmetic by two, predec
1637 
 
1638 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1639 
        test_zero_clear
1640 
        test_ovf_clear
1641 
        test_neg_clear
1642 
 
1643 
        test_h_gr32  long_dest er0
1644 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1645 
        test_gr_a5a5 2
1646 
        test_gr_a5a5 3
1647 
        test_gr_a5a5 4
1648 
        test_gr_a5a5 5
1649 
        test_gr_a5a5 6
1650 
        test_gr_a5a5 7
1651 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1652 
        ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1653 
        cmp.l   #0x69696969, @long_dest
1654 
        beq     .Llpredec2
1655 
        fail
1656 
.Llpredec2:
1657 
        mov     #0xa5a5a5a5, @long_dest
1658 
 
1659 
rotr_l_disp2_2:
1660 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1661 
        set_ccr_zero
1662 
 
1663 
        mov     #long_dest-8, er0
1664 
        rotr.l  #2, @(8:2, er0) ; shift right arithmetic by two, disp2
1665 
 
1666 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1667 
        test_zero_clear
1668 
        test_ovf_clear
1669 
        test_neg_clear
1670 
 
1671 
        test_h_gr32  long_dest-8 er0
1672 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1673 
        test_gr_a5a5 2
1674 
        test_gr_a5a5 3
1675 
        test_gr_a5a5 4
1676 
        test_gr_a5a5 5
1677 
        test_gr_a5a5 6
1678 
        test_gr_a5a5 7
1679 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1680 
        ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1681 
        cmp.l   #0x69696969, @long_dest
1682 
        beq     .Lldisp22
1683 
        fail
1684 
.Lldisp22:
1685 
        mov     #0xa5a5a5a5, @long_dest
1686 
 
1687 
rotr_l_disp16_2:
1688 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1689 
        set_ccr_zero
1690 
 
1691 
        mov     #long_dest-44, er0
1692 
        rotr.l  #2, @(44:16, er0)       ; shift right arithmetic by two, disp16
1693 
 
1694 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1695 
        test_zero_clear
1696 
        test_ovf_clear
1697 
        test_neg_clear
1698 
 
1699 
        test_h_gr32  long_dest-44 er0
1700 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1701 
        test_gr_a5a5 2
1702 
        test_gr_a5a5 3
1703 
        test_gr_a5a5 4
1704 
        test_gr_a5a5 5
1705 
        test_gr_a5a5 6
1706 
        test_gr_a5a5 7
1707 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1708 
        ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1709 
        cmp.l   #0x69696969, @long_dest
1710 
        beq     .Lldisp162
1711 
        fail
1712 
.Lldisp162:
1713 
        mov     #0xa5a5a5a5, @long_dest
1714 
 
1715 
rotr_l_disp32_2:
1716 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1717 
        set_ccr_zero
1718 
 
1719 
        mov     #long_dest-666, er0
1720 
        rotr.l  #2, @(666:32, er0)      ; shift right arithmetic by two, disp32
1721 
 
1722 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1723 
        test_zero_clear
1724 
        test_ovf_clear
1725 
        test_neg_clear
1726 
 
1727 
        test_h_gr32  long_dest-666 er0
1728 
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
1729 
        test_gr_a5a5 2
1730 
        test_gr_a5a5 3
1731 
        test_gr_a5a5 4
1732 
        test_gr_a5a5 5
1733 
        test_gr_a5a5 6
1734 
        test_gr_a5a5 7
1735 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1736 
        ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1737 
        cmp.l   #0x69696969, @long_dest
1738 
        beq     .Lldisp322
1739 
        fail
1740 
.Lldisp322:
1741 
        mov     #0xa5a5a5a5, @long_dest
1742 
 
1743 
rotr_l_abs16_2:
1744 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1745 
        set_ccr_zero
1746 
 
1747 
        rotr.l  #2, @long_dest:16       ; shift right arithmetic by two, abs16
1748 
 
1749 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1750 
        test_zero_clear
1751 
        test_ovf_clear
1752 
        test_neg_clear
1753 
 
1754 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
1755 
        test_gr_a5a5 1
1756 
        test_gr_a5a5 2
1757 
        test_gr_a5a5 3
1758 
        test_gr_a5a5 4
1759 
        test_gr_a5a5 5
1760 
        test_gr_a5a5 6
1761 
        test_gr_a5a5 7
1762 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1763 
        ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1764 
        cmp.l   #0x69696969, @long_dest
1765 
        beq     .Llabs162
1766 
        fail
1767 
.Llabs162:
1768 
        mov     #0xa5a5a5a5, @long_dest
1769 
 
1770 
rotr_l_abs32_2:
1771 
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
1772 
        set_ccr_zero
1773 
 
1774 
        rotr.l  #2, @long_dest:32       ; shift right arithmetic by two, abs32
1775 
 
1776 
        test_carry_clear                ; H=0 N=0 Z=0 V=0 C=0
1777 
        test_zero_clear
1778 
        test_ovf_clear
1779 
        test_neg_clear
1780 
 
1781 
        test_gr_a5a5 0           ; Make sure ALL general regs not disturbed
1782 
        test_gr_a5a5 1
1783 
        test_gr_a5a5 2
1784 
        test_gr_a5a5 3
1785 
        test_gr_a5a5 4
1786 
        test_gr_a5a5 5
1787 
        test_gr_a5a5 6
1788 
        test_gr_a5a5 7
1789 
        ; 1010 0101 1010 0101 1010 0101 1010 0101
1790 
        ;; -> 0110 1001 0110 1001 0110 1001 0110 1001
1791 
        cmp.l   #0x69696969, @long_dest
1792 
        beq     .Llabs322
1793 
        fail
1794 
.Llabs322:
1795 
        mov     #0xa5a5a5a5, @long_dest
1796 
 
1797 
.endif
1798 
.endif
1799 
        pass
1800 
 
1801 
        exit 0
1802 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.