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# Hitachi H8 testcase 'sub.l'
# mach(): h8300h h8300s h8sx
# as(h8300):    --defsym sim_cpu=0
# as(h8300h):   --defsym sim_cpu=1
# as(h8300s):   --defsym sim_cpu=2
# as(h8sx):     --defsym sim_cpu=3
# ld(h8300h):   -m h8300helf
# ld(h8300s):   -m h8300self
# ld(h8sx):     -m h8300sxelf
 
        .include "testutils.inc"
 
        start
 
.if (sim_cpu == h8sx)           ; 
sub_l_imm3:                     ; 3-bit immediate mode only for h8sx
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  sub.l #xx:3,eRd     ; Immediate 3-bit operand
        sub.l   #7:3, er0
 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
        test_h_gr32 0xa5a5a59e er0      ; sub result:   a5a5 - 7
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
sub_l_imm16:                    ; sub immediate 16-bit value
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  sub.l #xx:16,eRd    ; Immediate 16-bit operand
        sub.l   #0x1111:16, er0
 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
        test_h_gr16 0x9494 r0   ; sub result:   a5a5 - 1111
        test_h_gr32 0xa5a59494 er0      ; sub result:   a5a5 - 1111
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
.endif
 
sub_l_imm32:
        ;; sub.l immediate not available in h8300 mode.
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  sub.l #xx:32,Rd
        sub.l   #0x11111111, er0        ; Immediate 32-bit operand
 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
        test_h_gr32 0x94949494 er0      ; sub result:   a5a5a5a5 - 11111111
        test_gr_a5a5 1          ; Make sure other general regs not disturbed
        test_gr_a5a5 2
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
sub.l.reg:
        set_grs_a5a5            ; Fill all general regs with a fixed pattern
        ;;  fixme set ccr
 
        ;;  add.l Rs,Rd
        mov.l   #0x11111111, er1
        sub.l   er1, er0        ; Register operand
 
        ;; fixme test ccr       ; H=0 N=1 Z=0 V=0 C=0
        test_h_gr32 0x94949494 er0      ; sub result:   a5a5a5a5 - 11111111
        test_h_gr32 0x11111111 er1
        test_gr_a5a5 2          ; Make sure other general regs not disturbed
        test_gr_a5a5 3
        test_gr_a5a5 4
        test_gr_a5a5 5
        test_gr_a5a5 6
        test_gr_a5a5 7
 
        pass
 
        exit 0

Line No.	Rev	Author	Line
1	24	jeremybenn	`# Hitachi H8 testcase 'sub.l'`
2			`# mach(): h8300h h8300s h8sx`
3			`# as(h8300): --defsym sim_cpu=0`
4			`# as(h8300h): --defsym sim_cpu=1`
5			`# as(h8300s): --defsym sim_cpu=2`
6			`# as(h8sx): --defsym sim_cpu=3`
7			`# ld(h8300h): -m h8300helf`
8			`# ld(h8300s): -m h8300self`
9			`# ld(h8sx): -m h8300sxelf`
10
11			`.include "testutils.inc"`
12
13			`start`
14
15			`.if (sim_cpu == h8sx) ;`
16			`sub_l_imm3: ; 3-bit immediate mode only for h8sx`
17			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
18			`;; fixme set ccr`
19
20			`;; sub.l #xx:3,eRd ; Immediate 3-bit operand`
21			`sub.l #7:3, er0`
22
23			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
24			`test_h_gr32 0xa5a5a59e er0 ; sub result: a5a5 - 7`
25			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
26			`test_gr_a5a5 2`
27			`test_gr_a5a5 3`
28			`test_gr_a5a5 4`
29			`test_gr_a5a5 5`
30			`test_gr_a5a5 6`
31			`test_gr_a5a5 7`
32
33			`sub_l_imm16: ; sub immediate 16-bit value`
34			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
35			`;; fixme set ccr`
36
37			`;; sub.l #xx:16,eRd ; Immediate 16-bit operand`
38			`sub.l #0x1111:16, er0`
39
40			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
41			`test_h_gr16 0x9494 r0 ; sub result: a5a5 - 1111`
42			`test_h_gr32 0xa5a59494 er0 ; sub result: a5a5 - 1111`
43			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
44			`test_gr_a5a5 2`
45			`test_gr_a5a5 3`
46			`test_gr_a5a5 4`
47			`test_gr_a5a5 5`
48			`test_gr_a5a5 6`
49			`test_gr_a5a5 7`
50
51			`.endif`
52
53			`sub_l_imm32:`
54			`;; sub.l immediate not available in h8300 mode.`
55			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
56			`;; fixme set ccr`
57
58			`;; sub.l #xx:32,Rd`
59			`sub.l #0x11111111, er0 ; Immediate 32-bit operand`
60
61			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
62			`test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111`
63			`test_gr_a5a5 1 ; Make sure other general regs not disturbed`
64			`test_gr_a5a5 2`
65			`test_gr_a5a5 3`
66			`test_gr_a5a5 4`
67			`test_gr_a5a5 5`
68			`test_gr_a5a5 6`
69			`test_gr_a5a5 7`
70
71			`sub.l.reg:`
72			`set_grs_a5a5 ; Fill all general regs with a fixed pattern`
73			`;; fixme set ccr`
74
75			`;; add.l Rs,Rd`
76			`mov.l #0x11111111, er1`
77			`sub.l er1, er0 ; Register operand`
78
79			`;; fixme test ccr ; H=0 N=1 Z=0 V=0 C=0`
80			`test_h_gr32 0x94949494 er0 ; sub result: a5a5a5a5 - 11111111`
81			`test_h_gr32 0x11111111 er1`
82			`test_gr_a5a5 2 ; Make sure other general regs not disturbed`
83			`test_gr_a5a5 3`
84			`test_gr_a5a5 4`
85			`test_gr_a5a5 5`
86			`test_gr_a5a5 6`
87			`test_gr_a5a5 7`
88
89			`pass`
90
91			`exit 0`

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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [subl.s] - Blame information for rev 280