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[/] [openrisc/] [trunk/] [gnu-src/] [gdb-6.8/] [sim/] [testsuite/] [sim/] [h8300/] [subs.s] - Blame information for rev 280

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1 24 jeremybenn 
# Hitachi H8 testcase 'subs'
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# mach(): h8300h h8300s h8sx
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# as(h8300):    --defsym sim_cpu=0
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# as(h8300h):   --defsym sim_cpu=1
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# as(h8300s):   --defsym sim_cpu=2
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# as(h8sx):     --defsym sim_cpu=3
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# ld(h8300h):   -m h8300helf
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# ld(h8300s):   -m h8300self
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# ld(h8sx):     -m h8300sxelf
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        .include "testutils.inc"
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        # Instructions tested:
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        # subs #1, erd          ; 1 b 0 0erd
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        # subs #2, erd          ; 1 b 8 0erd
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        # subs #4, erd          ; 1 b 9 0erd
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        #
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        start
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.if (sim_cpu)                   ; 32 bit only
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subs_1:
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        set_grs_a5a5
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        set_ccr_zero
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        subs    #1, er0
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        test_cc_clear           ; subs should not affect any condition codes
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        test_h_gr32  0xa5a5a5a4 er0     ; result of subs #1
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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subs_2:
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        set_grs_a5a5
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        set_ccr_zero
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        subs    #2, er0
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        test_cc_clear           ; subs should not affect any condition codes
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        test_h_gr32  0xa5a5a5a3 er0     ; result of subs #2
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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subs_4:
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        set_grs_a5a5
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        set_ccr_zero
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        subs    #4, er0
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        test_cc_clear           ; subs should not affect any condition codes
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        test_h_gr32  0xa5a5a5a1 er0     ; result of subs #4
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        test_gr_a5a5 1          ; Make sure other general regs not disturbed
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        test_gr_a5a5 2
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        test_gr_a5a5 3
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        test_gr_a5a5 4
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        test_gr_a5a5 5
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        test_gr_a5a5 6
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        test_gr_a5a5 7
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        pass
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.endif
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        exit 0

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